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ics for communications sophisticated answering machine with echo cancellation sam - ec psb 4860 version 4.1 data sheet 2000-01-14 ds 1
for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com psb 4860 revision history: current version: 2000-01-14 previous version: page (in previous version) page (in current version) subjects (major changes since last revision) abm ? , aop ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, digitape ? , epic ? -1, epic ? -s, elic ? , falc ? 54, falc ? 56, falc ? -e1, falc ? -lh, idec ? , iom ? , iom ? -1, iom ? -2, ipat ? -2, isac ? -p, isac ? -s, isac ? -s te, isac ? -p te, itac ? , iwe ? , musac ? -a, octat ? -p, quat ? -s, sicat ? , sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4c, slicofi ? are registered trademarks of infineon technologies ag. ace ? , asm ? , asp ? , potswire ? , quadfalc ? , scout ? are trademarks of infineon technologies ag. edition 2000-01-14 published by infineon technologies ag, tr, balanstra?e 73, 81541 mnchen ? infineon technologies ag 2000. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you ? get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the infineon technologies ag, may only be used in life-support devices or systems 2 with the express written approval of the infineon technologies ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be en- dangered.
psb 4860 data sheet 3 2000-01-14 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.3 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.4 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.6 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.6.1 analog featurephone with digital answering machine . . . . . . . . . . . . . . .20 1.6.2 featurephone with digital answering machine for isdn terminal . . . . . .22 1.6.3 dect basestation with integrated digital answering machine . . . . . . . . .23 1.7 backward compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.1 functional units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.1.1 full duplex speakerphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.1.2 echo cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.1.3 echo suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.1.4 line echo canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 2.1.5 dtmf detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 2.1.6 cng detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 2.1.7 alert tone detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 2.1.8 universal tone detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 2.1.9 cpt detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 2.1.10 caller id decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.1.11 caller id sender . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.1.12 dtmf generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.1.13 speech coder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.1.14 speech decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 2.1.15 analog front end interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 2.1.16 digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 2.1.17 universal attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 2.1.18 automatic gain control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 2.1.19 equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 2.1.20 peak detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 2.2 memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 2.2.1 file definition and access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 2.2.2 user data word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 2.2.3 high level memory management commands . . . . . . . . . . . . . . . . . . . . .83 2.2.4 low level memory management commands . . . . . . . . . . . . . . . . . . . . . .95 2.2.5 execution time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 2.2.6 special notes on file commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 2.3 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 2.3.1 real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
psb 4860 data sheet 4 2000-01-14 2.3.2 sps control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 2.3.3 reset and power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 2.3.4 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 2.3.5 abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 2.3.6 revision register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 2.3.7 hardware configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 2.3.8 frame synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 2.3.9 clock tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 2.3.10 afe clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 2.3.11 restrictions and mutual dependencies of modules . . . . . . . . . . . . . . . . 106 2.3.12 emergency mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 2.4 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 2.4.1 iom ? -2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 2.4.2 ssdi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 2.4.3 analog front end interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 2.4.4 serial control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 2.4.5 memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 2.4.6 auxiliary parallel port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 3 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 3.1 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 3.2 hardware configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 3.3 read/write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 3.3.1 register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 3.3.2 register naming conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 4.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 4.3 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
psb 4860 data sheet 5 2000-01-14 figure 1: pin configuration of psb 4860. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 2: logic symbol of psb 4860. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 3: block diagram of psb 4860 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 4: analog full duplex speakerphone with digital answering machine . . . . 20 figure 5: stand-alone answering machine with data access via sci . . . . . . . . . . 21 figure 6: featurephone with answering machine for isdn terminal . . . . . . . . . . . 22 figure 7: dect basestation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 8: functional units - overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 9: functional units - recording a phone conversation . . . . . . . . . . . . . . . . 27 figure 10: functional units - simultaneous internal and external call . . . . . . . . . . . 28 figure 11: speakerphone - signal connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 12: speakerphone - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 13: echo cancellation unit - block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 14: echo cancellation unit - typical room impulse response . . . . . . . . . . . 31 figure 15: echo suppression unit - states of operation. . . . . . . . . . . . . . . . . . . . . . 32 figure 16: echo suppression unit - signal flow graph . . . . . . . . . . . . . . . . . . . . . . 33 figure 17: speech detector - signal flow graph . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 18: speech comparator - block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 19: speech comparator - acoustic echoes . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 20: speech comparator - interdependence of parameters . . . . . . . . . . . . . . 39 figure 21: echo suppression unit - automatic gain control. . . . . . . . . . . . . . . . . . . 42 figure 22: line echo cancellation unit - block diagram. . . . . . . . . . . . . . . . . . . . . . 45 figure 23: line echo cancellation unit - superior mode with shadow fir . . . . . . . 46 figure 24: dtmf detector - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 25: cng detector - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 26: alert tone detector - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 27: universal tone detector - block diagram . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 28: cpt detector - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 29: cpt detector - cooked mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 30: caller id decoder - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 31: caller id sender - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 32: dtmf generator - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 33: speech coder - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 34: vox detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 35: speech decoder - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 36: analog front end interface - block diagram . . . . . . . . . . . . . . . . . . . . . . 69 figure 37: digital interface - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 38: universal attenuator - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 39: automatic gain control unit - block diagram . . . . . . . . . . . . . . . . . . . . . 73 figure 40: equalizer - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 41: peak detector - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 42: memory management - data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 43: memory management - structure of message directory . . . . . . . . . . . . . 79
psb 4860 data sheet 6 2000-01-14 figure 44: memory management - structure of voice prompt directory. . . . . . . . . . 80 figure 45: audio file organization - example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 46: binary file organization - example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 47: phrase file organization - example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 48: operation modes - state chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 49: iom ? -2 interface - frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 50: iom ? -2 interface - frame start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 51: iom ? -2 interface - single clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 52: iom ? -2 interface - double clock mode . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 53: iom ? -2 interface - channel structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 54: ssdi interface - transmitter timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 55: ssdi interface - active pulse selection . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 56: ssdi interface - receiver timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 57: analog front end interface - frame structure . . . . . . . . . . . . . . . . . . . . 117 figure 58: analog front end interface - frame start . . . . . . . . . . . . . . . . . . . . . . . 118 figure 59: analog front end interface - data transfer . . . . . . . . . . . . . . . . . . . . . . 118 figure 60: status register read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 61: data read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 62: register write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 63: configuration register read access . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 64: configuration register write access or register read command . . . . 122 figure 65: aram/dram interface - connection diagram . . . . . . . . . . . . . . . . . . . 127 figure 66: aram/dram interface - read cycle timing . . . . . . . . . . . . . . . . . . . . . 128 figure 67: aram/dram interface - write cycle timing . . . . . . . . . . . . . . . . . . . . . 129 figure 68: aram/dram interface - refresh cycle timing. . . . . . . . . . . . . . . . . . . 129 figure 69: eprom interface - connection diagram . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 70: eprom interface - read cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 71: parallel flash memory interface - connection diagram. . . . . . . . . . . . . 131 figure 72: parallel flash memory interface - multiple devices . . . . . . . . . . . . . . . . 132 figure 73: parallel flash memory interface - command write . . . . . . . . . . . . . . . . 133 figure 74: parallel flash memory interface - address write . . . . . . . . . . . . . . . . . . 133 figure 75: parallel flash memory interface - data write . . . . . . . . . . . . . . . . . . . . 134 figure 76: parallel flash memory interface - data read . . . . . . . . . . . . . . . . . . . . 134 figure 77: serial flash - connection to single tc 58 a 040 f . . . . . . . . . . . . . . . . 135 figure 78: serial flash - connection to single at 45 db 041 . . . . . . . . . . . . . . . . 135 figure 79: serial flash - connection to multiple tc 58 a 040 f . . . . . . . . . . . . . . . 136 figure 80: auxiliary parallel port - multiplex mode . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 81: input/output waveforms for ac-tests . . . . . . . . . . . . . . . . . . . . . . . . . . 301 figure 82: oscillator circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 figure 83: ssdi/iom ? -2 interface - bit synchronization timing . . . . . . . . . . . . . . . 306 figure 84: ssdi/iom ? -2 interface - frame synchronization timing . . . . . . . . . . . . 306 figure 85: ssdi interface - strobe timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 figure 86: serial control interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
psb 4860 data sheet 7 2000-01-14 figure 87: analog front end interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 figure 88: memory interface - dram read access . . . . . . . . . . . . . . . . . . . . . . . . 311 figure 89: memory interface - dram write access . . . . . . . . . . . . . . . . . . . . . . . . 312 figure 90: memory interface - dram refresh cycle . . . . . . . . . . . . . . . . . . . . . . . 313 figure 91: memory interface - eprom read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 figure 92: memory interface - samsung command write . . . . . . . . . . . . . . . . . . . 315 figure 93: memory interface - samsung address write . . . . . . . . . . . . . . . . . . . . . 316 figure 94: memory interface - samsung data write . . . . . . . . . . . . . . . . . . . . . . . . 317 figure 95: memory interface - samsung data read . . . . . . . . . . . . . . . . . . . . . . . . 318 figure 96: auxiliary parallel port - multiplex mode . . . . . . . . . . . . . . . . . . . . . . . . . 319 figure 97: reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
psb 4860 data sheet 8 2000-01-14 table 1: pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 2: signal summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 3: echo cancellation unit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 4: speech detector parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 5: speech comparator parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 6: attenuation control unit parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 7: sps output encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 8: automatic gain control parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 9: fixed gain parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 10: speakerphone control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 11: selection of the mode of the line echo canceller . . . . . . . . . . . . . . . . . . .47 table 12: line echo cancellation unit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 13: dtmf detector control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 14: dtmf detector results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 15: dtmf detector parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 16: cng detector registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 17: cng detector result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 18: alert tone detector registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 19: alert tone detector results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 20: universal tone detector registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 21: universal tone detector results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 22: cpt detector result. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 23: cpt detector registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 24: caller id decoder modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 25: caller id decoder status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 26: caller id decoder registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 27: caller id sender modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 28: caller id sender status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 29: caller id sender registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 30: dtmf generator registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 table 31: speech coder status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 32: speech coder control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 33: speech coder - gap detector control registers . . . . . . . . . . . . . . . . . . . .62 table 34: vox detector registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 table 35: speech coder - data transfer via sci. . . . . . . . . . . . . . . . . . . . . . . . . . . .65 table 36: speech decoder registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 table 37: speech decoder - data transfer via sci . . . . . . . . . . . . . . . . . . . . . . . . . .68 table 38: analog front end interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 table 39: digital interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 table 40: universal attenuator registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 table 41: automatic gain control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 table 42: equalizer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 table 43: peak detector registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
psb 4860 data sheet 9 2000-01-14 table 44: memory management registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 45: memory management status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 46: memory management parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 47: initialize memory parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 48: initialize memory results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 49: initialize memory parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 50: activate memory parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 51: activate memory results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 52: activate memory result interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 53: read data parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 54: read data results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 55: open file parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 56: open next free file parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 57: open next free file results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 58: seek parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 59: cut file parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 60: delete multiple files parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 61: compress file parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 62: memory status parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 63: memory status results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 64: garbage collection parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 65: write file descriptor parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 66: read file descriptor parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 67: access file descriptor results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 68: read data parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 69: read data results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 70: write data parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 71: set address parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 72: dma read parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 table 73: dma write parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 74: block erase parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 75: execution times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 76: real time clock registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 77: sps register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 78: power down bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 79: interrupt source summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 80: hardware configuration checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 81: frame synchronization selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 82: dependencies of modules - 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 83: dependencies of modules - 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 84: file command classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 85: module weights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 table 86: command words for emergency mode data transfer . . . . . . . . . . . . . . 110
psb 4860 data sheet 10 2000-01-14 table 87: ssdi vs. iom ? -2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 table 88: iom ? -2 interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 table 89: ssdi interface register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 table 90: control of als amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 table 91: analog front end interface register . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 table 92: analog front end interface clock cycles . . . . . . . . . . . . . . . . . . . . . . . . .118 table 93: command words for register access . . . . . . . . . . . . . . . . . . . . . . . . . . .122 table 94: address field w for configuration register write . . . . . . . . . . . . . . . . . .122 table 95: address field r for configuration register read . . . . . . . . . . . . . . . . . .123 table 96: supported memory configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 table 97: address line usage (aram/dram mode) . . . . . . . . . . . . . . . . . . . . . . .127 table 98: refresh frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 table 99: address line usage (samsung mode). . . . . . . . . . . . . . . . . . . . . . . . . . .131 table 100: flash memory command summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 table 101: pin functions for serial flash interface. . . . . . . . . . . . . . . . . . . . . . . . . .135 table 102: memory interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 table 103: auxiliary parallel port mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . .137 table 104: static mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 table 105: multiplex mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 table 106: interrupt mask definition for parallel port . . . . . . . . . . . . . . . . . . . . . . . .139 table 107: signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 table 108: status register update timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
semiconductor group 11 11.99 psb 4860 1overview general general combined with an analog front end the provides a solution for embedded or stand alone answering machine applications. together with a standard microcontroller for analog telephones these two chips form the core of a featurephone with full duplex speakerphone and answering machine capab ilities. the chip features recording by digitape ? , a family of high performance algorithms. messages recorded with digitape ? can be played back with variable speed without pitch alteration. messages recorded with a higher bitrate can be converted into messages with a lower bitrate arbitrarily. the psb 4860 version 4.1 supports three members of digitape ? : 10.3 kbit/s, 5.6 kbit/s and 3.3 kbit/s. furthermore the , version 4.1 features a full duplex speakerphone, a caller id decoder, dtmf recognition and generation and call progress tone detection. a programmable band-pass can be used to detect special tones besides the standard call progress tones. the frequency response of cheap microphones or loudspeakers can be corrected by a programmable equalizer. messages and user data can be stored in aram/dram or flash memory which can be directly connected to the . the also supports a voice prompt eprom for fixed announcements. the provides an iom ? -2 compatible interface with up to three channels for speech data. alternatively to the iom ? -2 compatible interface the supports a simple serial data interface (ssdi) with separate strobe signals for each direction (linear pcm data, one channel). a separate interface is used for a glueless connection to the dual channel codec sam- afe (psb 4851). the chip is programmed by a simple four wire serial control interface and can inform the microcontroller of new events by an interrupt signal. for data retention the supports a power down mode where only the real time clock and the memory refresh (in case of aram/dram) are operational. the supports interface pins to +5 v input levels.
p-mqfp-80-1 data sheet 12 2000-01-14 sophisticated answering machine with echo cancellation sam psb 4860 version 4.1 cmos type package psb 4860 p-mqfp-80-1 1.1 features digital functions high performance recording by digitape ? selectable compression rate (3.3, 5.6 or 10.3 kbit/s) variable playback speed support for dram/aram or flash memory (5v, 3.3v) x1, x4 and x8 aram/dram supported optional voice prompt eprom up to four serial or parallel flash devices supported (atmel, toshiba, samsung) audio data transfer via serial control interface (sci) possible full duplex speakerphone by acoustic echo cancellation dtmf generation and detection call progress tone detection caller id decoder caller id sender direct memory access real time clock equalizer for transducer/microphone frequency response correction automatic gain control automatic timestamp universal tone detector three data channels (iom ? -2 compatible interface) auxiliary parallel port with optional interrupt generation ultra low power refresh mode emergency shut-down (fast parameter saving into flash device) backward compatible with psb 4860 v2.1 (hardware and software)
psb 4860 data sheet 13 2000-01-14 1.2 pin configuration (top view) figure 1 pin configuration of 110 20 21 30 40 41 60 50 61 70 80 v dda xtal 1 xtal 2 osc 1 osc 2 v ssa sclk sdr v dd afedd afedu v dd v ss v dd v ss afefs afeclk fsc du/dx dd/dr dxst drst v dd v ss dcl w /fwe frdy vprd /fcle ras /foe cas 1 /fcs sps 0 sps 1 v dd v ss md 1 /sdi md 2 /sdo ma 3 ma 2 ma 1 ma 0 md 7 /cs 3 md 6 /cs 2 md 5 /cs 1 md 4 /cs 0 md 3 v dd v ss v dd v ss v ss v ss ro v dd ma 4 ma 5 ma 6 v dd ma 8 v ss ma 15 v ss ma 7 ma 9 ma 10 v dd ma 12 ma 13 ma 14 v ss ma 11 v ddp rst clk v ss md 0 /sclk v ddp int sdx cs cas 0 /ale sam-ec psb 4860
psb 4860 data sheet 14 2000-01-14 1.3 pin definitions and functions table 1 pin definitions and functions pin no. p-mqfp-80 symbol dir. 1) reset function 7, 15, 21, 29, 39, 49, 58, 61, 67, 73 v dd -- power supply (3.0 v - 3.6 v ) power supply for logic. 1 v dda -- power supply (3.0 v - 3.6 v) power supply for clock generator. 4 v ssa -- power supply (0 v) ground for clock generator. 9, 16, 22, 30, 40, 48, 57, 59, 60, 78, 66, 72 v ss -- power supply (0 v) ground for logic and interface. 17 afefs o l analog frontend frame sync: 8 khz frame synchronization signal for the communication with the analog front end (psb 4851). 18 afeclk o l analog frontend clock: clock signal for the analog front end (6.912 mhz). 19 afedd o l analog frontend data downstream: data output to the analog frontend. 20 afedu i - analog frontend data upstream: data input from the analog frontend. 79 rst i - reset: active high reset signal. 23 fsc i - data frame synchronization: 8 khz frame synchronization signal (iom ? -2 and ssdi mode). 24 dcl i - data clock: data clock of the serial data of the iom ? -2 compatible and ssdi interface.
psb 4860 data sheet 15 2000-01-14 26 dd/dr i /od i - iom ? -2 compatible mode: receive data from iom ? -2 controlling device. ssdi mode: receive data of the strobed serial data interface. 25 du/dx i /od o/ od - iom ? -2 compatible mode: transmit data to iom ? -2 controlling device. ssdi mode: transmit data of the strobed serial data interface. 27 dxst o l dx strobe: strobe for dx in ssdi interface mode. 28 drst i - dr strobe: strobe for dr in ssdi interface mode. 14 cs i- chip select: select signal of the serial control interface (sci). 11 sclk i - serial clock: clock signal of the serial control interface (sci). 13 sdr i - serial data receive: data input of the serial control interface (sci). 12 sdx o/ od h serial data transmit: data output of the serial control interface (sci). 10 int o/ od h interrupt new status available. table 1 pin definitions and functions
psb 4860 data sheet 16 2000-01-14 52 53 54 55 62 63 64 65 68 69 70 71 74 75 76 77 ma 0 ma 1 ma 2 ma 3 ma 4 ma 5 ma 6 ma 7 ma 8 ma 9 ma 10 ma 11 ma 12 ma 13 ma 14 ma 15 i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o l 2) l 2) l 2) l 2) l 2) l 2) l 2) l 2) l 2) l 2) l 2) l 2) l 2) l 2) l 2) l 2) memory address 0-15: multiplexed address outputs for aram, dram access. non-multiplexed address outputs for voice prompt eprom. auxiliary parallel port: general purpose i/o. 42 43 44 45 46 47 50 51 md 0 / sclk md 1 /sdi md 2 /sdo md 3 md 4 /cs 0 md 5 /cs 1 md 6 /cs 2 md 7 /cs 3 i /o i /o i /o i /o i /o i /o i /o i /o - - - - - - - - aram/dram or samsung flash: memory data bus. serial flash memory (toshiba, atmel): serial interface signals and predecoded chip select lines. 35 36 cas 0 /ale cas 1 / fcs o o h 3) aram, dram: column address strobe for memory bank 0 or 1. flash memory: address latch enable for address lines a 16 - a 23 . chip select signal for flash memory 34 ras /foe oh 3) aram, dram: row address strobe for both memory banks. flash memory: output enable signal for flash memory. table 1 pin definitions and functions
psb 4860 data sheet 17 2000-01-14 33 vprd / fcle oh 3) aram, dram: read signal for voice prompt eprom. flash memory: command latch enable for flash memory. 32 w /fwe oh 3) aram, dram: write signal for all memory banks. flash memory: write signal for flash memory. 31 frdy i - flash memory ready input for ready/busy signal of flash memory 5 6 osc 1 osc 2 i o - z auxiliary oscillator: oscillator loop for 32.768 khz crystal. 8clki- alternative afeclk source 13,824 mhz 2 3 xtal 1 xtal 2 i o - z oscillator: xtal 1 : external clock or input of oscillator loop. xtal 2 : output of oscillator loop for crystal. 37 38 sps 0 sps 1 o o l l multipurpose outputs: general purpose, speakerphone, address lines or status 56 ro o - reserved output must be left open. 41, 80 nc - - not connected 1) i = input o = output od = open drain 2) these lines are driven low with 102 a (typical) until the mode (address lines or auxiliary port) is defined. 3) these lines are driven high with 100 a (typical) during reset. table 1 pin definitions and functions
psb 4860 data sheet 18 2000-01-14 1.4 logic symbol 1 figure 2 logic symbol of du/dx dd/dr dcl fsc sdx sdr sclk cs iom ? -2 sci afeclk afefs afedu afedd psb ma 0 -ma 15 md 0 -md 7 cas 0 / ale cas 1 / fcs foe ras / vprd/ fcle w / fwe memory v dda v dd v ss osc 2 osc 1 xtal 1 xtal 2 rst ssdi 4851 int frdy dxst drst clk
psb 4860 data sheet 19 2000-01-14 1.5 functional block diagram figure 3 block diagram of du/dx dd/dr dcl fsc sdx sdr sclk cs afeclk afefs afedu afedd ma 0 -ma 15 md 0 -md 7 cas 0 / ale cas 1 / fcs foe ras / vprd / fcle w / fwe osc 2 osc 1 xtal 1 xtal 2 rst dsp memory interface reset and timing unit data interface control interface analog front end interface int frdy dxst drst
psb 4860 data sheet 20 2000-01-14 1.6 system integration the combined with an analog front end (psb 4851) can be used in a variety of applications. this combination offers outstanding features like full duplex speakerphone and emergency operation. some applications are given in the following sections. 1.6.1 analog featurephone with digital answering machine figure 4 shows an example of an analog telephone system. the telephone can operate during power failure by line powering. in this case only the handset and ringer circuit are active. all other parts of the chipset are shut down leaving enough power for the external microcontroller to perform basic tasks like keyboard monitoring. for answering machine operation the voice data can be stored in a flash memory devices. in addition, voice prompts can be stored in the flash as well. alternatively, an aram or dram can be used to store the voice data. then, the voice prompts can be stored eprom which can be connected to the /psb 4851 additionally. the microcontroller can use the memory attached to the /psb 4851 to store and retrieve binary data. figure 4 analog full duplex speakerphone with digital answering machine flash memory microcontroller 077-3445 line tip/ ring psb 4851 sci
psb 4860 data sheet 21 2000-01-14 the psb 4860 does not need to be directly connected to a flash or dram but can use the sci interface to store and get its data. an example is shown in figure 5 . figure 5 stand-alone answering machine with data access via sci flash memory microcontroller 077-3445 line tip/ ring psb 4851 sci
psb 4860 data sheet 22 2000-01-14 1.6.2 featurephone with digital answering machine for isdn terminal figure 6 shows an isdn featurephone. all voice data is transferred by the iom ? -2 compatible interface. the is programmed by the sci interface. the microcontroller can access the memory attached to the . this is useful for storing system parameters or phonebook entries. figure 6 featurephone with answering machine for isdn terminal flash psb 4860 microcontroller 077-3445 iom ? -2 s 0 -bus power controller peb 2023 psb 21381/2 sam-ec scout-s
psb 4860 data sheet 23 2000-01-14 1.6.3 dect basestation with integrated digital answering machine figure 7 shows a dect basestation based on the /psb 4851 chipset. in this application it is possible to service both an external call and an internal call at the same time. for programming the serial control interface (sci) is used while voice data is transferred via the iom ? -2 compatible interface (ssdi/iom ? -2). figure 7 dect basestation flash memory microcontroller 077-3445 antenna ssdi/iom ? -2 sci burstmode controller dect hf line tip/ ring psb 4851
psb 4860 data sheet 24 2000-01-14 1.7 backward compatibility the psb 4860 version 4.1 is backwards compatible with the psb 4860 v2.1 and v3.1 with respect to: pin configuration supply voltage signal levels start-up sequence after reset register definition 1) all of the additional features of the psb 4860 version 4.1 are enabled by previously unused bits of the hardware configuration registers, the read/write registers or reserved command opcodes. therefore the psb 4860 version 4.1 can be used as a drop-in replacement for the psb 4860 v3.1 if the following checklist is observed: 1. update version register inquiry (if present) for new version 2. ensure no invalid (for v2.1 or v3.1) commands, registers or programming values are used the psb 4860 version 4.1 can be used as a drop-in replacement for the psb 4860 v2.1 if the following is taken care of additionally: 1. ensure no low level mmu command is used in application 2. use voice prompt tool (formatter) for version 4.1 (e.g. sprompt, aprompt, tprompt) 3. read/write data accesses are not used to clear an interrupt 4. dtmf receiver has different handling of dtc bit and expects slightly differnt timing of the tones 5. an improved oscillator makes new start-up tests necessary furthermore, there are a few changes which should have no impact on backwards compatibility: 1. the status bits are updated faster 2. the dram refresh starts as soon as register cctl is written (aram/dram specified) 3. the bit eie in the file command register fcmd does not exist any more. the value at this bit position is ignored. this bit is not needed any more as the psb 4860 v3.1 and v4.1 executes file commands as soon as possible anyway. note: if application of v2.1 uses low level mmu commands (e.g. for in-system reloading of voice prompts) then this code must be changed to work properly for v4.1. 1) exceptions are: satt2:ds, sagx2:speedh and sagr2:speedh
psb 4860 data sheet 25 2000-01-14 2 functional description functional units functional units the contains several functional units that can be combined with almost no restrictions to perform a given task. figure 8 gives an overview of the important functional units. figure 8 functional units - overview each unit has one or more signal inputs (denoted by i). most units have at least one signal output (denoted by s). any input i can be connected to any signal output s. in addition to the signals shown in figure 8 there is also the signal s 0 (silence), which is dtmf generator dtmf detector speech coder speaker- phone cid decoder speech decoder cpt/utd detector line line micro- loud- ssdi/iom ? -2 iom ? -2 s 1 s 3 s 5 s 23 s 11 s 12 s 10 s 9 s 13 s 4 s 2 s 24 s 6 signal summation: signal sources: s 1 ,...,s 24 in out speaker phone i 1 i 2 i 3 line side acoustic side memory sci i 1 i 1 i 1 i 2 i 3 i 1 i 2 i 3 channel 3 channel 1 i 3 i 4 i 1 i 2 i 1 i 2 i 3 i 1 i 2 i 3 i 1 i 2 i 1 alert tone detector cng detector i 1 i 1 universal attenuator i 1 s 14 line echo canceller i 1 i 2 s 15 agc i 1 i 2 s 17 equalizer i 1 s 18 s 16 iom ? -2 channel 2 i 1 i 2 i 3 s 7 s 8 cid sender s 22 peak detector i 1
psb 4860 data sheet 26 2000-01-14 useful at signal summation points. table 2 lists the available signals within the according to their reference points. table 2 signal summary signal description s 0 silence s 1 analog line input (channel 1 of psb 4851 interface) s 2 analog line output (channel 1 of psb 4851 interface) s 3 microphone input (channel 2 of psb 4851 interface) s 4 loudspeaker/handset output (channel 2 of psb 4851 interface) s 5 serial interface input, channel 1 s 6 serial interface output, channel 1 s 7 serial interface input, channel 2 s 8 serial interface output, channel 2 s 9 dtmf generator output s 10 dtmf generator aux iliary output s 11 speakerphone output (acoustic side) s 12 speakerphone output (line side) s 13 speech decoder output s 14 universal attenuator output s 15 line echo canceller output s 16 automatic gain control output (after gain stage) s 17 automatic gain control output (before gain stage) s 18 equalizer output s 22 caller id sender output s 23 serial interface input, channel 3 s 24 serial interface output, channel 3
psb 4860 data sheet 27 2000-01-14 the following figures show the connections for two typical states during operation. units that are not needed are not shown. inputs that are not needed are connected to s 0 which provides silence (denoted by 0). in figure 9 a hands-free phone conversation is currently in progress. the speech coder is used to record the signals of both parties. the alert tone detector is used to detect an alerting tone of an off-hook caller id request while the cid decoder decodes the actual data transmitted in this case. figure 9 functional units - recording a phone conversation alert tone detector speech coder speaker- phone cid decoder line echo canceller line line micro- loud- in out speaker phone line side acoustic side memory sci 0 0 0 0 0 0 agc
psb 4860 data sheet 28 2000-01-14 in figure 10 a phone conversation using the speakerphone is in progress. one party is using the base station of a dect system while the other party is using a mobile handset. at the same time an external call is serviced by the answering machine. in the current state a message (recorded or outgoing) is being played back. in this case the dtmf detector is used to detect signals for remote access while the cpt detector is used to determine the end of the external call. figure 10 functional units - simultaneous internal and external call speaker- phone speech decoder line line micro- loud- ssdi/iom ? -2 in out speaker phone line side acoustic side memory sci 0 0 0 channel 1 0 0 00 0 dtmf detector cpt decoder line echo canceller equalizer
psb 4860 data sheet 29 2000-01-14 2.1 functional units in this section the functional units of the are described in detail. the functional units can be individually enabled or disabled. 2.1.1 full duplex speakerphone the speakerphone unit (figure 11 ) is attached to four signals (microphone, loudspeaker, line out and line in). the two input signals (microphone, line in) are preceded by signal summation points. figure 11 speakerphone - signal connections internally, this unit can be divided into an echo cancellation unit and an echo suppression unit (figure 12 ). the echo cancellation unit provides the attenuation g c while the echo suppression unit provides the attenuation g s . the total attenuation att of the speakerphone is therefore att=g c +g s . figure 12 speakerphone - block diagram the echo cancellation unit estimates that part of the signal at the microphone that originates from the loudspeaker. this part is then subtracted from the signal at the microphone. this technique allows a full-duplex speakerphone. speakerphone s 11 s 12 a c o u s t i c s i d e l i n e s i d e i 2 i 1 i 3 i 4 microphone loudspeaker line out line in echo cancellation line out microphone loudspeaker line in echo suppression g c g s
psb 4860 data sheet 30 2000-01-14 the echo suppression unit attenuates the receive or transmit path dependent on what path is active. without the echo cancellation unit and by using a high attenuation of the echo suppression unit, the echo suppression unit provides a half-duplex speakerphone. if the echo cancellation unit is active but cannot provide all of the required attenuation itself, the echo suppression unit can be used to provide additional attenuation. the echo cancellation must be disabled during recording or playback of speech data but the echo suppression unit can run simultenously. this allows half-duplex speakerphone operation even when recording or playback is on-going. 2.1.2 echo cancellation a simplified block diagram of the echo cancellation unit is shown in figure 13 . figure 13 echo cancellation unit - block diagram the echo cancellation unit consists of a finite impulse response filter (fir) that models the expected acoustic echo, an nlms based adaptation unit and a control unit. the expected echo is subtracted from the actual input signal of the microphone. if the model is exact and the echo does not exceed the length of the filter then the echo can be cancelled completely. however, even if this ideal state can be achieved for one moment the acoustic echo usually changes over time. therefore the nlms unit continuously adapts the coefficients of the fir filter. this adaptation process is steered by the control unit. as an example, the adaptation is disabled as long as double talk is detected by the control unit. furthermore the control unit informs the echo suppression unit about the achieved echo return loss. table 3 shows the registers associated with the echo cancellation unit. microphone loudspeaker - fir filter nlms control line out line in
psb 4860 data sheet 31 2000-01-14 the length of the fir filter can be varied from 127 to 511 taps (15.875ms to 63.875ms). the taps are grouped into blocks. each block contains 64 taps. the performance of the fir filter can be enhanced by prescaling some or all coefficients of the fir filter. prescaling a coefficient means the coefficient gets multiplied by a constant. the advantage of prescaling is an enhanced precision and consequently an enhanced echo cancellation. the disadvantage is a reduced echo cancellation performance if the signal exceeds the maximal coefficient value. more precisely, if a coefficient at tap t i is scaled by a factor c i then the level of the echo (room impulse response) must not exceed max/c i (max: maximum pcm value). figure 14 shows an example of a typical room impulse response. figure 14 echo cancellation unit - typical room impulse response in this example, the echo never exceeds 0.5 of the maximum value. furthermore after time t 0.25 the echo never exceeds 0.25 of the maximum value. therefore all coefficients can be scaled by a factor of 2 and all coefficients for taps corresponding to times after t 0.25 can be scaled by a factor of 4. the echo cancellation unit provides three parameters for scaling coefficients. the first parameter gs determines a factor c i =2 gs for all coefficients. the second parameter fb determines the first block, for which an additional parameter ps contributes to the factor c i =2 gs+ps . this feature can be used for different default settings like large or small rooms. table 3 echo cancellation unit registers register # of bits name comment saelen 9 len length of fir filter saeatt 15 att attenuation reduction during double-talk saegs 3 gs global scale (all blocks) saeps1 3 ps partial scale (for blocks >= saeps2:fb) saeps2 3 fb first block affected by partial scale t a 0.5 0.25 t 0.25
psb 4860 data sheet 32 2000-01-14 2.1.3 echo suppression the echo suppression unit can be in one of three states: transmit state receive state idle state in transmit state the microphone signal drives the line output while the line input is attenuated. in receive state the loudspeaker signal is driven by the line input while the microphone signal is attenuated. in idle state both signal paths are active with evenly distributed attenuation. it can be prevendted that the echo suppression unit goes into the idle state figure 15 echo suppression unit - states of operation line out line in microphone loudspeaker idle state line out line in microphone loudspeaker receive state line out line in microphone loudspeaker transmit state
psb 4860 data sheet 33 2000-01-14 figure 16 shows the signal flow graph of the echo suppression unit in more detail. figure 16 echo suppression unit - signal flow graph the attenuation control performs the switching between the three possible states by using the attenuation stages ghx and ghr. actually, state switching is controlled by the speech comparators scas and scls and by the speech detectors sdx and sdr. the gain control units agcx, agcr, lgax, and lgar are used to achieve proper signal levels for each state. all blocks are programmable. thus, the telephone set can be optimized and adjusted to the particular geometrical and acoustical environment. the following sections discuss the blocks of the echo suppression unit in detail. scls scas sdx sdr agcr agcx attenuation control line out microphone loudspeaker lgax lgar line in ghx ghr
psb 4860 data sheet 34 2000-01-14 2.1.3.1 speech detector for each signal source a speech detector (sdx, sdr) is available. the speech detectors are identical but can be programmed individually. figure 17 shows the signal flow graph of a speech detector. figure 17 speech detector - signal flow graph the first three units (lim, lp1, pd) are used for preprocessing the signal while the actual speech detection is performed by the background noise monitor. background noise monitor the tasks of the noise monitor are to differentiate voice signals from background noise, even if it exceeds the voice level, and to recognize voice signals without any delay. therefore the background noise monitor consists of the low-pass filter 2 (lp2) and the offset in two separate branches. basically it works on the burst-characteristic of the speech: voice signals consist of short peaks with high power (bursts). in contrast, background noise can be regarded approximately stationary from its average power. low-pass filter 2 provides different time constants for noise (non-detected speech) and speech. it determines the average of the noise reference level. in case of background noise the level at the output of lp2 is approximately the level of the input. as in the other branch an additional offset off is added to the signal, the comparator signals noise. at speech bursts the digital signals arriving at the comparator via the offset branch change faster than those via the lp2-branch. if the difference exceeds the offset off, the lim lp1 pd lp2 off lp1 pds pdn lp2s lp2n lp2l background noise monitor signal preprocessing - lim
psb 4860 data sheet 35 2000-01-14 comparator signals speech. therefore the output of the background noise monitor is a digital signal indicating speech (1) or noise (0). a small fade constant (lp2n) enables fast settling of lp2 to the average noise level after the end of speech recognition. however, a too small time constant for lp2n can cause rapid charging to such a high level that after recognizing speech the danger of an unwanted switching back to noise exists. it is recommended to choose a large rising constant (lp2s) so that speech itself charges the lp2 very slowly. generally, it is not recommended to choose an infinite lp2s because then approaching the noise level is disabled. during continuous speech or tones the lp2 will be charged until the limitation lp2l is reached. then the value of lp2 is frozen until a break discharges the lp2. this limitation permits transmission of continuous tones and ? music on hold ? . the offset stage represents the estimated difference between the speech signal and averaged noise. signal preprocessing as described in the preceding chapter, the background noise monitor is able to discriminate between speech and noise. in very short speech pauses e.g. between two words, however, it changes immediately to non-speech, which is equal to noise. therefore a peak detection is required in front of the noise monitor. the main task of the peak detector (pd) is to bridge the very short speech pauses during a monolog so that this time constant has to be long. furthermore, the speech bursts are stored so that a sure speech detection is guaranteed. but if no speech is recognized the noise low-pass lp2 must be charged faster to the average noise level. in addition, the noise edges are to be smoothed. therefore two time constants are necessary. as the peak detector is very sensitive to spikes, the low-pass lp1 filters the incoming signal containing noise in a way that main spikes are eliminated. due to the programmable time constant it is possible to refuse high-energy sibilants and noise edges. to compress the speech signals in their amplitudes and to ease the detection of speech, the signals have to be companded logarithmically. hereby, the speech detector should not be influenced by the system noise which is always present but should discriminate between speech and background noise. the limitation of the logarithmic amplifier can be programmed via the parameter lim. lim is related to the maximum pcm level. a signal exceeding the limitation defined by lim is getting amplified logarithmically, while very smooth system noise below is neglected. it should be the level of the minimum system noise which is always existing; in the transmit path the noise generated by the telephone circuitry itself and in receive direction the level of the first bit which is stable without any speech signal at the receive path. table 4 shows the parameters for the speech detector.
psb 4860 data sheet 36 2000-01-14 the input signal of the speech detector can be connected to either the input signal of the echo suppression unit (as shown for sdx) or the output of the associated agc (as shown for sdr). this can be selected with bits sdx and sdr of table 10 . table 4 speech detector parameters parameter # of bytes range comment lim 1 0 to -95 db limitation of log. amplifier off 1 0 to 95 db level offset up to detected noise pds 1 1 to 2000 ms peak decrement pd1 (speech) pdn 1 1 to 2000 ms peak decrement pd1 (noise) lp1 1 1 to 2000 ms time constant lp1 lp2s 1 2 to 250 s time constant lp2 (speech) lp2n 1 1 to 2000 ms time constant lp2 (noise) lp2l 1 0 to 95 db maximum value of lp2
psb 4860 data sheet 37 2000-01-14 2.1.3.2 speech comparators (sc) the echo suppression unit has two identical speech comparators (scas, scls). each comparator can be programmed individually to accommodate the different system characteristics of the acoustic interface and the line interface. as scas and scls are identical, the following description holds for both scas and scls. the sc has two input signals sx and sr, which map to microphone/loudspeaker for scas and line in/line out for scls. the speech comparator decides whether the signal coming in on sr is only an echo from the signal outgoing on sx or a real speech activity. the result is then interpreted by the attenuation control of figure 16 . in general, the sc works according to the following equation: therefore, scas controls the switching to transmit state and scls controls the switching to receive state. switching is done only if sx exceeds sr by at least the expected acoustic level enhancement v. this level enhancement is divided into two parts: g and gd. a block diagram of the sc is shown in figure 18 . figure 18 speech comparator - block diagram at both inputs, logarithmic amplifiers compress the signal range. hence, only logarithmic levels are on both paths and after the signals have been processed, logarithmic levels on both paths are compared. if sx > sr + v then switch state g gds gdn pds pdn sx sr log. amp. base gain gain reserve peak decrement log. amp. pds pdn peak decrement
psb 4860 data sheet 38 2000-01-14 the main task of the comparator is to control the echo. the internal coupling due to the direct sound and mechanical resonances is covered by g. the external coupling, mainly caused by the acoustic feedback, is controlled by gd/pd. an example for direct sound (1) and acoustic feedback (2) is illustrated in figure 19 . figure 19 speech comparator - acoustic echoes the base gain g corresponds to the terminal couplings of the complete telephone. thus, g is the measured or calculated level enhancement between the receive and the transmit input of the sc. to control the acoustic feedback two parameters are necessary: gd represents the actual reserve on the measured g. together with the peak decrement (pd), the echo behavior at the acoustic side is modeled: after speech has ended there is a short time during which hard couplings through the mechanics and resonances and the direct echo are present. till the end of that time ( ? t ), the level enhancement v must be at least equal to g to prevent clipping caused by these internal couplings. after that time ( ? t ), only the acoustic feedback is present. this coupling, however, is reduced by air attenuation. for this in general the longer the delay, the smaller the echo being valid. this echo behavior is taken care of by the decrement rate pd. 1 2
psb 4860 data sheet 39 2000-01-14 figure 20 speech comparator - interdependence of parameters according to figure 19 , a compromise between the reserve gd and the decrement rate pd has to be made: a smaller reserve (gd) above the level enhancement g requires a longer time to decrease (pd). it is easy to overshout the other side but the intercommunication is harder because after the end of the speech, the level of the estimated echo has to be exceeded. in contrast, with a higher reserve (gd*) it is harder to overshout continuous speech or tones, but a faster intercommunication is supported because of a stronger decrement (pd*). two pairs of coefficients, gds/pds when speech is detected, and gdn/pdn in case of noise, offer a different echo handling for speech and non-speech. with speech, even if very strong resonances are present, the performance will not be worsened by the high gds needed. only when speech is detected, a high reserve prevents clipping. the time ? t (determined by parameter et) after speech ends, the parameters of the comparator are switched to the ? noise ? values. if both sets of the parameters are equal, et has no effect. table 5 speech comparator parameters parameter # of bytes range comment g1 ? 48 to + 48 db base gain gds 1 0 to 48 db gain reserve (speech) t db ? t gd* gd pd* pd rx-speech rx-noise g g
psb 4860 data sheet 40 2000-01-14 2.1.3.3 attenuation control the attenuation control unit performs state switching by controlling the attenuation stages ghx and ghr. in receive state, the attenuation g is completely switched to ghx. in transmit state, the attenuation g is completely switched to ghr. in idle state, both ghx and ghr attenuate by g/2. state switching depends on the signals of one speech comparator and the corresponding speech detector. the attenuation g actually provided by the attenuation stages ghr and ghx is the attenuation determined by the parameter att minus the attenuation reported by the echo cancellation unit (g = att - g c ). additional (fixed) attenuation on the transmit and receive path is also influenced by the automatic gain control stages agcx and agcr, respectively. while each state is associated with the programmed attenuation, the time t sw it takes to reach the steady-state attenuation after a state switch can be programmed. the time t sw depends on a programmable decay rate sw and the current attenuation g by the formula . if the current state is either transmit or receive and no speech on either side has been detected for time t tw then the idle state is entered. to smoothen the transition, the attenuation is incremented (decremented) by ds until the evenly distribution g/2 for both ghx and ghr is reached. table 6 summarizes the parameters for the attenuation unit. pds 1 0.025 to 6 db/ms peak decrement (speech) gdn 1 0 to 48 db gain reserve (noise) pdn 1 0.025 to 6 db/ms peak decrement (noise) et 1 0 to 992 ms time to switch from speech to noise parameters table 6 attenuation control unit parameters parameter # of bytes range comment tw 1 0 ms to 4096 ms t tw to return to idle state att 1 0 to 95 db attenuation of both echo cancellation and echo suppression ds 1 0.6 to 680 ms/db decay speed (to idle state) sw 1 0.0052 to 10 ms/db decay rate (used for t sw ) table 5 speech comparator parameters parameter # of bytes range comment t sw sw g =
psb 4860 data sheet 41 2000-01-14 note: in addition, attenuation is also influenced by the automatic gain control stages (agcx, agcr) in order to keep the total loop attenuation constant. note: by programming parameter ds to 0xff idle mode is disabled and the speakerphone will remain in the last state. this parameter must be set before enabling the speakerphone. 2.1.3.4 echo suppression status output the psb 4860 can report the current state of the echo suppression unit to ease optimization of the parameter set of the echo suppression unit. in this case the sps 0 and sps 1 pins are set according to table 7 . furthermore the controller can read the current value of the sps pins by reading register spsctl. 2.1.3.5 loudhearing the speakerphone unit can also be used for controlled loudhearing. this is enabled by setting bit md in register sctl. if loudhearing mode is enabled, the loudspeaker amplifier of the psb 4851 (als) is used instead of ghr (figure 16 ) when appropriate to avoid oscillation. to use this feature, the psb 4851 must be programmed to allow als override. the als field within the afe control register afectl defines the value sent to the psb 4851 if attenuation is necessary (see specification of the psb 4851). 2.1.3.6 amplifiers with automatic gain control the echo suppression unit has two identical automatic gain control units agcx and agcr both referred to as agc in this section. whether the automatic gain control agc amplifies or attenuates depends on whether the signal level is above or below the threshold level defined by parameter com. the threshold is relative to the maximum pcm-value and thus negative. the parameters ag_gain and ag_att determine the maximal amplification and attenuation, respectively. the bold line in figure 21 gives an example for the steady-state output level of the agc as a function of the input level. table 7 sps output encoding sps 0 sps 1 echo suppression unit state 0 0 no echo suppression operation 01receive 1 0 transmit 1 1 idle
psb 4860 data sheet 42 2000-01-14 figure 21 echo suppression unit - automatic gain control for reasons of physiological acceptance, the agc gain is automatically reduced in case of continuous background noise (e.g. by ventilators). the reduction is programmed via the nols parameter. when the noise level exceeds the threshold determined by nois, the amplification will be reduced by the same amount the noise level is above the threshold. the regulation speed is controlled by speedh for signal amplitudes above the threshold and speedl for amplitudes below. usually speedh will be chosen to be at least 10 times faster than speedl. an additional low pass with time constant lp is provided to avoid an immediate response of the agc to very short signal bursts. the time constant of the low pass should not be selected longer than 4 ms in order to avoid unstable behavior. if the speech detector sdx detects noise or the receive path is active, agcx freezes its current attenuation and the last gain setting is used. regulation starts with this value as soon as sdx detects speech and the receive path is inactive. likewise, if sdr detects noise or the transmit path is active, agcr freezes its current attenuation and the last gain setting is used. regulation starts with this value as soon as sdr detects speech and the transmit path is inactive. the current gain/attenuation of the agc can be read at any time (ag_cur). when the agc has been disabled, the initial gain used immediately after enabling the agc can be programmed. table 8 shows the parameters of the agc. com ag_att ag_gain agc input level agc output level max. pcm -10 db -20 db -10 db -20 db example: com ag_gain ag_att = = = -30 db 15 db 20 db
psb 4860 data sheet 43 2000-01-14 note: there are two sets of parameters, one for agcx and one for agcr. note: by setting ag_gain to 0 db a limitation function can be realized with the agc. 2.1.3.7 amplifiers with fixed gain each signal path features an additional amplifier (lgax, lgar) that can be set to a fixed gain. these amplifiers should be used for the basic amplification in order to avoid saturation in the preceding stages. table 9 describes the only parameter of this stage. 2.1.3.8 mode control table 10 shows the registers used to determine the signal sources and the speakerphone mode. table 8 automatic gain control parameters parameter # of bytes range comment ag_init 1 -95 db to 95db initial agc gain/attenuation com 1 0 to ? 95 db compare level rel. to max. pcm-value ag_att 1 0 to -95 db attenuation range ag_gain 1 0 to 48 db gain range ag_cur 1 -95 db to 95 db current gain/attenuation speedl 1 0.25 to 62.5 db/s change rate for lower levels speedh 1 2 to 500 db/s change rate for higher levels nois 1 0 to ? 95 db threshold for agc-reduction by background noise lp 1 0.025 to 16 ms agc low pass time constant table 9 fixed gain parameters parameter # of bytes range comment lga 1 -30 db to 12 db always active table 10 speakerphone control registers register # of bits name comment sctl 1 ens echo suppression unit enable sctl 1 enc echo cancellation unit enable sctl 1 md speakerphone or loudhearing mode
psb 4860 data sheet 44 2000-01-14 sctl 1 agx agcx enable sctl 1 agr agcr enable sctl 1 sdx sdx input tap sctl 1 sdr sdr input tap afectl 4 als als value for loudhearing ssrc1 5 i1 input signal 1 (microphone) ssrc1 5 i2 input signal 2 (microphone) ssrc2 5 i3 input signal 3 (line in) ssrc2 5 i4 input signal 4 (line in) table 10 speakerphone control registers
psb 4860 data sheet 45 2000-01-14 2.1.4 line echo canceller the contains an adaptive line echo cancellation unit for the cancellation of near end echoes. the unit has three modes. normal mode: the maximum echo length considered is 4 ms. this mode is always avail- able. extended mode: the maximum echo length considered is 24 ms. this mode cannot be used while the speech encoder, the acoustic echo cancellation unit or slow playback is active. superior mode: the maximum echo length considered is 4 ms. this mode is always available. by using an additional shadow filter, the echo cancellation quality is improved. the line echo cancellation unit is especially useful in front of the various detectors (dtmf, cpt, etc.). a block diagram is shown in figure 22 . figure 22 line echo cancellation unit - block diagram input i 2 is usually connected to the line input while input i 1 is connected to the outgoing signal. in normal mode the adaptation process is controlled by the three parameters min, att and mgn. adaptation takes place only if both of the following conditions hold: 1. 2. with the first condition, adaptation to small signals can be avoided. the second condition avoids adaptation during double talk. the parameter att represents the echo loss provided by external circuitry. the adaptation stops if the power of the received signal (i2) exceeds the power of the expected signal (i1-att) by more than the margin mgn. in extended mode, adaptation is enabled all the time. + - adaptive filter i 2 s 15 i 1 i1 min > i1 i2 ?attmgn + ?0 >
psb 4860 data sheet 46 2000-01-14 figure 23 line echo cancellation unit - superior mode with shadow fir the basic idea of the superior mode is shown in figure 23 . the shadow fir filter on the left hand side gets its coefficients adapted similar to the adaptive filter of the line echo canceller in normal mode. for cancelling the line echo, however, the fir filter on the right hand side is used. when the quality of this fir filter is excelled by the quality of the shadow fir filter, the coefficients of the shadow fir filter are copied to the fir on the right hand side. more formally, the coefficients of the shadow fir filter are adapted (see unit ? adapt coeff ? in figure 23 ) if similar to normal mode, the following two conditions hold: 1. 2. in this case, att is already the difference between external echo loss and margin (att superior = att normal - mgn normal ) so that the condition is actually the same as for normal mode. the parameter att should be adjusted accordingly. note that att can now be negative. the coefficients are copied from the shadow fir filter to the actually used fir filter (see unit ? copy coeff. ? in figure 23 ) if 1. currently the adaptation of the shadow fir filter is in progress and at least one of the following two conditions holds: 2. the attenuation of the shadow fir filter atts is better than the attenuation of the actually used fir filter atta by a margin mgn. note that parameter mgn has now a different meaning than in normal mode 3. the current attenuation atts of the shadow fir is better than at any time since last update according to condition 2. + - filter fir i 2 s 15 i 1 fir shadow filter adapt copy coeff. coeff. i1 min > i1 i2 ?att ?0 > atts atta ?mgn > atts t () max atts t 1 ? () atts last time condition 2 has been valid () ,, () >
psb 4860 data sheet 47 2000-01-14 table 11 shows the registers associated with the line echo canceller. the adaptation of the coefficients can be stopped by setting bit as in register lecctl. this holds for all three modes of the line echo canceller. furthermore for superior mode, also the copying of the coefficients from the shadow fir is disabled. the different modes can be selected by setting the bits md and cm as indicated by table 12 . table 12 selection of the mode of the line echo canceller table 11 line echo cancellation unit registers register # of bits name comment relevant mode lecctl 1 en line echo canceller enable all lecctl 1 md line echo canceller mode lecctl 1 cm compatibility mode lecctl 1 as adaptation stop all lecctl 5 i2 input signal selection for i 2 all lecctl 5 i1 input signal selection for i 1 all leclev 15 min minimal power for signal i 1 normal and sup. lecatt 15 att externally provided attenuation (i 1 to i 2 ) normal and sup. lecmgn 15 mgn margin normal and sup. md cm mode 00normal mode 0 1 superior mode 1 - extended mode
psb 4860 data sheet 48 2000-01-14 2.1.5 dtmf detector the contains an dtmf detector that recognizes the sixteen standard dtmf tones. figure 24 shows a block diagram of the dtmf detector. the results of the detector are available in the status and a dedicated result register. these registers can be read by the external controller via the serial control interface (sci). figure 24 dtmf detector - block diagram table 13 to 15 show the associated registers. as soon as a valid dtmf tone is recognized, the status word and the dtmf tone code are updated (table 14 ). dtv is set when a dtmf tone is currently recognized and cleared when no dtmf tone is recognized or the detector is disabled. the code for the dtmf tone is provided in register ddctl. dtc is valid when dtv is set and until the next incoming dtmf tone. the registers ddtw and ddlev contain the parameters for detection (table 15 ). table 13 dtmf detector control register register # of bits name comment ddctl 1 en dtmf detector enable ddctl 5 i1 input signal selection table 14 dtmf detector results register # of bits name comment status 1 dtv dtmf code valid ddctl 5 dtc dtmf tone code table 15 dtmf detector parameters register # of bits name comment ddtw 15 twist twist for dtmf recognition ddlev 6 min minimum signal level to detect dtmf tones dtmf sci i 1 detector
psb 4860 data sheet 49 2000-01-14 2.1.6 cng detector the calling tone (cng) detector can detect the standard ca lling tones of fax machines or modems. this helps to distinguish voice messages from data transfers. the result of the detector is available in the status register that can be read by the external controller via the serial control interface (sci). the cng detector consists of two band-pass filters with fixed center frequency of 1100 hz and 1300 hz. figure 25 cng detector - block diagram table 16 shows the available parameters. for a calling tone being detected, both the programmed minimum time and the minimum signal level must be exceeded. furthermore the input signal resolution can be reduced by the res parameter. then the signal noise below the threshold res is not regarded. this can be useful in a noisy environment at low signal levels although the accuracy of the detection decreases. as soon as a valid tone is detected, the status word of the is updated. the status bits are defined as follows: note: status:cng is cleared only by disabling the module. table 16 cng detector registers register # of bits name comment cngctl 1 en cng detector enable cngctl 5 i1 input signal selection cnglev 16 min minimum signal level cngbt 16 time minimum time of signal burst cngres 16 res input signal resolution table 17 cng detector result register # of bits name comment status 1 cng fax/modem calling tone detected cng detector sci i 1 1100 hz 1300 hz
psb 4860 data sheet 50 2000-01-14 2.1.7 alert tone detector the alert tone detector can detect the standard alert tones (2130 hz and 2750 hz) for caller id protocols. the results of the detector are provided in the status register and register atdctl0. these registers can be read by the external controller via the serial control interface (sci). figure 26 alert tone detector - block diagram as soon as a valid alert tone is recognized, the status word of the and the code for the detected combination of alert tones are updated (table 19 ). with on hook mode selected, the end of the alert tone can be detected faster. on hook mode assumes that there is no speech signal present. table 18 alert tone detector registers register # of bits name comment atdctl0 1 en alert tone detector enable atdctl0 5 i1 input signal selection atdctl1 1 md detection of dual tones or single tones atdctl1 1 dev maximum deviation (0.5% or 1.1%) atdctl1 1 onh on hook mode atdctl1 8 min minimum signal level to detect alert tones table 19 alert tone detector results register # of bits name comment status 1 atv alert tone detected atdctl0 2 atc alert tone code alert tone sci i 1 detector
psb 4860 data sheet 51 2000-01-14 2.1.8 universal tone detector the universal tone detector can be used instead of the cpt detector to detect special tones which are not covered by the standard cpt band-pass. figure 27 shows the functional block diagram. a figure 27 universal tone detector - block diagram initially, the input signal is filtered by a programmable band-pass (center frequency cf and band width bw ). both the in-band signal (upper path) and the out-of-band signal are determined (lower path) and the absolute value is calculated. both signals are furthermore filtered by a limiter and a low-pass. all signal samples (absolute values) below a programmable limit lim are set to zero and all other signal samples are diminished by lim . the purpose of the limiter is to increase noise robustness. after the limiter stages both signals are filtered by a fixed low pass. the evaluation logic block determines when to set and when to reset the status bit status:utd. the status bit will be set if both of the following conditions hold for at least time ttone without breaks exceeding time tb1 : 1. the in-band signal exceeds a programmable level lev 2. the difference of the in-band and the out-of-band signal exceeds delta the status bit will be reset if at least one of these conditions is violated by at least time tgap without breaks exceeding tb2 . the times tb1 and tb2 help to reduce the effects of sporadic dropouts. example: ttone is set to 100 ms and tb1 is set to 4 ms. i 1 evaluation logic sci programmable band-pass lp lp limit limit |x| |x|
psb 4860 data sheet 52 2000-01-14 the conditions are met for 30ms, then violated for 3ms and then met again for 80 ms. in this case the break of 3ms is ignored, because it does not exceed the allowed break time tb1. therefore the status bit will be set after 100 ms. table 20 summarizes the associated registers. the result is available in the status register (table 21 ). note: the utd bit is at the same position as the cpt bit. therefore the cpt detector and the utd must not run at the same time. table 20 universal tone detector registers register # of bits name comment utdctl 1 en band-pass enable utdctl 5 i1 input signal selection utdbw 15 bw bandwidth of band-pass utdcf 16 cf center frequency of band-pass utdlim 15 lim limiter limit utdlev 15 lev minimum signal level (in-band) utdlev 15 delta minimum difference (in-band, out-of-band) utdtmt 8 ttone minimum time to set status bit utdtmt 8 tb1 maximum break time for ttone utdtmg 8 tgap minimum time to reset status bit utdtmg 8 tb2 maximum break time for tgap table 21 universal tone detector results register # of bits name comment status 1 utd tone detected
psb 4860 data sheet 53 2000-01-14 2.1.9 cpt detector the selected signal is monitored continuously for a call progress tone. the cpt detector consists of a band-pass and an optional timing checker (figure 28 ). figure 28 cpt detector - block diagram the cpt detector can be used in two modes: raw and cooked. in raw mode, the occurrence of a signal within the frequency range, time and energy limits is directly reported. the timing checker is bypassed and therefore the does not interpret the length or any interval of the signal. in cooked mode, the number and duration of signal bursts are interpreted by the timing checker. a signal burst followed by a gap is called a cycle. cooked mode requires a minimum of two cycles. the cpt flag is set with the first burst after the programmed number of cycles has been detected. the cpt flag remains set until the unit is disabled or speech is detected, even if the conditions are not met anymore. in this mode the cpt is modeled as a sequence of identical bursts separated by gaps with identical length. the can be programmed to accept a range for both the burst and the gap. it is also possible to specify a maximum aberration of two consecutive bursts and gaps. figure 29 shows the parameters for a single cycle (burst and gap). figure 29 cpt detector - cooked mode the status bit is defined as follows: timing band-pass sci (status) i 1 300-640 hz checker t bmax t bmin t gmin t gmax
psb 4860 data sheet 54 2000-01-14 cpt is not affected by reading the status word. it is automatically reset when the unit is disabled. table 23 shows the control register for the cpt detector. if any condition is violated during a sequence of cycles the timing checker is reset and restarts with the next valid burst. note: in cooked mode cpt is set with the first burst after the programmed number of cycles has been detected. if cpttr:num = 2, then cpt is set with the third signal burst. note: the number of cycles must be set to zero in raw mode. note: the utd bit is at the same position as the cpt bit. therefore the cpt detector and the utd must not run at the same time. table 22 cpt detector result register # of bits name comment status 1 cpt cp tone currently detected [300 hz; 640 hz] table 23 cpt detector registers register # of bits name comment cptctl 1 en unit enable cptctl 1 md mode (cooked, raw) cptctl 5 i1 input signal selection cptmn 8 minb minimum time of a signal burst (t bmin ) cptmn 8 ming minimum time of a signal gap (t gmin ) cptmx 8 maxb maximum time of a signal burst (t bmax ) cptmx 8 maxg maximum time of a signal gap (t gmax ) cptdt 8 difb maximum difference between consecutive bursts cptdt 8 difg maximum difference between consecutive gaps cpttr 3 num number of cycles (cooked mode), 0 (raw mode) cpttr 8 min minimum signal level to detect tones cpttr 4 sn minimal signal-to-noise ratio
psb 4860 data sheet 55 2000-01-14 2.1.10 caller id decoder the caller id decoder is basically a 1200 baud modem (fsk, demodulation only). the bit stream is formatted by a subsequent uart and the data is available in a data register along with status information (figure 30 ). figure 30 caller id decoder - block diagram the fsk demodulator supports two modes according to table 24 . the appropriate mode is detected automatically. the cid decoder does not interpret the data received. each byte received is placed into the cidctl register (table 26 ). the status byte of the is updated (table 25 ). cia and cd are cleared when the unit is disabled. in addition, cia is cleared when cidctl0 is read. table 24 caller id decoder modes mode mark (hz) space (hz) comment 1 1200 2200 bellcore 2 1300 2100 v.23 table 25 caller id decoder status register # of bits name comment status 1 cia cid byte received status 1 cd carrier detected table 26 caller id decoder registers register # of bits name comment cidctl0 1 en unit enable cidctl0 1 dot drop out tolerance during mark or seizure sequence cidctl0 1 cm compatibility mode cidctl0 5 i1 input signal selection uart fsk demod. sci (status, data) i 1 (bellcore, v.23)
psb 4860 data sheet 56 2000-01-14 when the cid unit is enabled, it waits for a programmable number of continuous mark bits (cidctl1:nmb). these mark bits may optionally be preceded by a channel seizure signal consisting of a series of alternating space and mark signals. if such a channel seizure sequence is present it must consist of at least cidctl1:nmss alternating mark and space bits. once the programmed number of continuous mark bits has been received the sets the carrier detect bit status:cd. the interpretation of the data, including message type, length and checksum is completely left to the controller. the cid unit should be disabled as soon as the complete information has been received as it cannot detect the end of the transmission by itself. there are two alternative caller id decoders. with bit cm cleared, the standard caller id decoder is selected, which is compatible to psb 4860 versions 2.1 and 3.1. the standard called id decoder requires a seizure sequence. with cm set to 1, the improved caller id decoder is selected, which provides a higher twist tolerance and improved noise immunity, does not require a seizure sequence, and allows to select the drop out tolerance. the drop out tolerance is selected by bit dot of register cidctl0. then, drop outs during a mark sequence do not necessarily cause that the cid detection looses its carrier sequence, but the received mark sequence can be recognized although there are drop outs. the same holds for a seizure sequence. this behavior meets the bellcore test specification. if drop out tolerance is enabled, the six registers cidmf1 to cidmf6 have to be programmed prior to use of this feature. note that these registers are undefined after recompression. the registers cidmf1 to cidmf6 must contain all possible message formats, which can be transmitted after the mark sequence, and these registers must not contain any other value. for bellcore for example, the valid message formats are 04 h , 06 h , 80 h and 82 h so that registers cidmf1 to cidmf6 may contain 04 h , 06 h , 80 h , 82 h , 82 h and 82 h . note: some caller id mechanism may require additional external components for dc decoupling. these tasks must be handled by the controller. note: the controller is responsible for selecting and storing parts of the cid as needed. note: the caller id decoder cannot be enabled at the same time as the caller id sender. cidctl0 8 data last cid data byte received cidctl1 5 nmss number of mark/space sequences necessary for successful detection of carrier. cidctl1 5 nmb number of mark bits necessary before space of first byte after carrier detected. cidctl1 6 min minimum signal level for cid detection. table 26 caller id decoder registers register # of bits name comment
psb 4860 data sheet 57 2000-01-14 2.1.11 caller id sender the caller id sender is a 1200 baud modem (fsk, modulation only). the byte data stream is formatted by a uart and then modulated (figure 31 ). figure 31 caller id sender - block diagram the fsk modulator supports two modes according to table 27 . the cid sender can send a programmable number of seizure bits, followed by an also programmable number of mark bits prior to the first data byte. the sender starts transmission once it is enabled. the status byte of the is updated (table 28 ). bit cir is set, when a new byte for transmission can be written to cisdata:data. if no new data byte has been written in time (i.e. at the beginning of the next start bit) then the caller id sender automatically sends stop bits and sets the status bit cis. cis and cir are cleared when the unit is disabled or the data register cisdata is written. table 27 caller id sender modes mode mark (hz) space (hz) comment 1 1200 2200 bellcore 2 1300 2100 v.23 table 28 caller id sender status register # of bits name comment status 1 cir cid byte request status 1 cis stop bits are sent table 29 caller id sender registers register # of bits name comment cisctl 1 en unit enable cisctl 1 md modulation mode uart fsk mod. s 22 sci (bellcore, v.23)
psb 4860 data sheet 58 2000-01-14 note: the caller id sender cannot be activated at the same time as the caller id decoder. cisdata 8 data next data byte to be transmitted cislev 15 lev transmit signal level cisszr 15 seiz number of seizure bits cismrk 15 mark number of mark bits table 29 caller id sender registers register # of bits name comment
psb 4860 data sheet 59 2000-01-14 2.1.12 dtmf generator the dtmf generator can generate single or dual tones with programmable frequency and level. this unit is primarily used to generate the common dtmf tones but can also be used for signalling or other user defined tones. a block diagram is shown in figure 32 . figure 32 dtmf generator - block diagram the two frequency generators and level adjustment stages are identical. there are two modes for programming the generators, cooked mode and raw mode. in cooked mode, the standard dtmf frequencies are generated by programming a single 4 bit code. in raw mode, the frequency of each generator can be programmed individually by a separate register. the unit has two outputs which provide the same signal but with individually programmable attenuation. table 30 shows the parameters of this unit. note: dgf1 and dgf2 are undefined when cooked mode is used and must not be written. table 30 dtmf generator registers register # of bits name comment dgctl 1 en enable for generators dgctl 1 md mode (cooked/raw) dgctl 4 dtc dtmf code (cooked mode) dgf1 15 frq1 frequency of generator 1 dgf2 15 frq2 frequency of generator 2 dgl 7 lev1 signal level of generator 1 dgl 7 lev2 signal level of generator 2 dgatt 8 att1 attenuation of s 9 dgatt 8 att2 attenuation of s 10 f 1 f 2 generator generator lev1 lev2 att2 s 9 s 10 att1
psb 4860 data sheet 60 2000-01-14 2.1.13 speech coder the speech coder (figure 33 ) has two input signals i 1 and i 2 . the first signal (i 1 ) is fed to the coder while the second signal (i 2 ) is used as a reference signal for voice controlled recording. the signal i 1 can be coded by either a 3.3 kbit/s, 5.6 kbit/s or 10.3 kbit/s coder. figure 33 speech coder - block diagram the data rates 10.3 kbit/s and 5.6 kbit/s are fixed rates. the data rate 3.3 kbit/s is an average rate that can actually vary between 740 bit/s and 4.8 kbit/s. the rate currently achieved heavily depends on the energy of the incoming signal. while silence is encoded with 740 bit/s, high energy bursts require 4.8 kbit/s. this implies that for a voice prompt consisting of only one word, the compression rate tends to be approximately 4.8 kbit/s. furthermore if an automatic gain control agc is used, the agc may increase the signal power in such a way that silence is not recognized as silence. then, the compression rate also tends to approximate 4.8 kbit/s. data is written initially at the beginning of a file and the file pointer is advanced as needed. in case of any memory error (e.g. memory full) a file error is indicated and the coder is disabled. the controller must subsequently close the file. the file can be played back, though. the coder ? s compression rate can be switched on the fly. however, it may take up to 60 ms until the switch is executed. no audio data is lost during switching. the signal i 2 is first filtered by a low pass lp with programmable time constant and then compared to a reference level min. if the filtered signal exceeds min, then the status bit sd (table 31 ) is set immediately. if the filtered signal has been smaller than min for a programmable time time then the status bit sd is reset. the coder can be enabled in permanent mode or in voice recognition mode. in permanent mode (bit vc is set to 0), the coder starts immediately and compresses all input data continuously. the current state of the status bit sd does not affect the coder. in voice recognition mode (bit vc is set to 1), the coder is automatically started on the first transition of the status bit from 0 to 1. once the coder has started it remains active until disabled. 10300 bit/s i 2 i 1 memory min lp 3300 bit/s 5600 bit/s vox gap sci sci
psb 4860 data sheet 61 2000-01-14 the coder can optionally use silence gap coding. this feature can reduce the bit rate dramatically if there are long periods of silence in the incoming data stream. the gap bit in the status register is set when a gap is detected and the speech coder performs gap coding. this feature is only available for compression rates 5.6 and 10.3 kbit/s, and thus cannot be used to influence compression rate in 3.3 kbit/s mode. furthermore the speech coder contains a vox detector that can distinguish voice from signals with constant energy (noise, silence, sine signals). the result of this detector is available by the bit vox of the status register. the operation of the speech coder is defined according to table 32 . table 31 speech coder status register # of bits name comment status 1 sd speech detected status 1 gap a gap is detected during recording status 1 vox noise, silence, constant or periodic signal detected table 32 speech coder control registers register # of bits name comment scctl 1 en enable speech coder scctl 1 gap enable gap coding scctl 2 q0, q1 recording quality scctl 1 vc voice controlled recording scctl 1 vox vox detection enable scctl 5 i1 input signal 1 selection scctl 5 i2 input signal 2 selection scct2 8 min minimal signal level for speech detection scct2 8 time minimum time for reset of sd scct3 7 lp time constant for low-pass scct3 8 gapt minimum time for gap
psb 4860 data sheet 62 2000-01-14 the gap detector consists of a speech detector and a subsequent timer. a gap is detected whenever the speech detector detects no speech for at least time gapt. the speech detector has the same signal flow graph and parameters as the speech detectors sdx or sdr of the speakerphone. table 33 shows the registers that hold these parameters. table 33 speech coder - gap detector control registers register # of bits name comment scgap1 7 lp2l maximum value of lp2 scgap1 7 lim limitation of log. amplifier scgap2 8 lp1 time constant lp1 scgap2 7 off level offset up to detected noise scgap3 8 pdn peak decrement pd1 (noise) scgap3 8 lp2n time constant lp2 (noise) scgap4 8 pds peak decrement pd1 (speech) scgap4 7 lp2s time constant lp2 (speech)
psb 4860 data sheet 63 2000-01-14 the task of the vox detector is to distinguish between a signal containing voice and high energy signals called vox containing just noise or periodic signals (e.g. sine waves). the general idea how to do this is to distinguish between signals with different crest factors. the crest factor is the difference between the signal ? s peak and root-mean- square power. furthermore, also signals with low power are classified as vox. the vox detector is illustrated in figure 34 . figure 34 vox detector the vox detector uses a hierarchical approach with three levels of hierarchy: 1. slice level a slice is a 9ms sample of the signal (bars in figure 34 ). for each slice the power of the signal is calculated. 2. segment level a segment consists of a programmable number (flen) of slices. each segment is classified as either a low power, a high power non-voice or a voice segment depending on the power and distribution of the slices. 3. frame level a frame consists of a programmable number (nframes) of segments. for each frame the status of the vox bit is reconsidered based on the information from the segments. for each segment the difference between the largest and the smallest power is calculated. this can be considered as a pseudo-crest factor. for the first segment, the pseudo-crest factor would be the difference between slice 5 and slice 3. furthermore for each segment the number n of slices that exceed the programmable limit (power) is determined. for the first segment slices 2, 4 and 5 exceed the limit. therefore n is 3. now for each segment the following result is generated: if n is smaller than the programmable parameter rpowb, then this segment contains a low power signal and the segment is classified as low power. if n is at least rpowb but t p power frame 1 frame 2 slice segment
psb 4860 data sheet 64 2000-01-14 the pseudo-crest factor is smaller than the parameter crest then the segment is also classified as low power. otherwise the segment is classified as voice. now the segments are combined into frames and for each frame the following calculation is performed: if at least cvf adjacent segments contain voice then the vox bit is reset. the internal timer is reset. if the vox bit was cleared before, nothing happens. a new frame will be started immediately. if at most rlpf segments are classified as low power segments and at least rvf segments are classified as voice segments, then the vox bit is reset because the frame contains voice. the timer is also reset and the next frame is processed. otherwise, the internal timer is incremented. if the timer has reached the value time then the vox bit is set and the next frame is processed. table 34 shows the registers for the vox detector. table 34 vox detector registers register # of bits name comment scvox1 7 nframes number of segments within one frame scvox1 7 cvf minimum number of adjacent voice segments scvox2 7 rlpf minimum number of low power segments for vox scvox2 7 rvf minimum number of voice segments for voice scvox3 15 power power reference level for slices (noise vs. signal) scvox4 15 crest pseudo-crest factor for slices (vox/voice) scvox5 7 rpowb minimum number of voice slices within segment scvox5 7 time minimum time to set vox bit scvox6 11 flen number of slices within a segment
psb 4860 data sheet 65 2000-01-14 the psb 4860 offers the possib ility to transfer the speech data via sci. then, no aram/ dram or flash needs to be connected to the psb 4860. to use this feature, the sci bit in register sdctl must be set. the speech coder writes the speech data into register scdata. bit da in register status indicates when new data has been written to scdata and the microcontroller must then read this data. when the microcontroller reads the data, the da bit is cleared. table 35 shows the registers involved. table 35 speech coder - data transfer via sci note: even when the coder is currently being disabled, some last data of the current block might still have to be transferred via sci. the microcontroller must go on with the transfers as long as the da bit indicates new data. note: the data format is different to when aram or flash memory is used. the compression rate increases by 0.4 kbit/s in case the date rate 10.3 kbit/s or 5.6 kbit/s is used and by 0.2 kbit/s in case the date rates 3.3 kbit/s is used. register # of bits name comment sdctl 1 sci speach data transfer via sci status 1 da new data available scdata 16 data speech data
psb 4860 data sheet 66 2000-01-14 2.1.14 speech decoder the speech decoder (figure 35 ) decompresses the data previously coded by the speech coder unit and delivers a standard 128 kbit/s data stream. figure 35 speech decoder - block diagram the decoder supports fast (1.5 and 2.0 times) and slow (0.5 times) motion independent of the selected quality. the data rate, with which the decoder requests input data, changes accordingly. for messages that have been recorded with gap coding the decoder offers two additional options. firstly, the gaps can be skipped during decoding. with this option, gaps are reduced to a single audio block (30 ms) independently of their original length. secondly, gaps can be replayed as silence or with a noise with programmable level. the noise level is relative to the level when the message had been recorded. the spectrum of the replayed noise is similar to the recoded noise. table 36 shows the registers for the speech decoder. data reading starts at the location of the current file pointer. the file pointer is updated during speech decoding. if the end of the file is reached, the decoder is automatically disabled. the automatically resets sdctl:en at this point. if the speed shall be changed on the fly (i.e. while the decoder is enabled) the cs bit must be set at the same time. table 36 speech decoder registers register # of bits name comment sdctl 1 en enable speech decoder sdctl 1 cs change speed sdctl 1 cp gap compression sdctl 1 cn gap comfort noise sdctl 2 speed selection of playback speed sdct2 15 cn gap comfort noise level s 13 memory 10300 bit/s 3300 bit/s 5600 bit/s
psb 4860 data sheet 67 2000-01-14 note: the last 90 ms of the file are not played back. therefore an additional 90 ms of speech should be recorded. if tail-cut is used then it is recommended to cut 3 blocks (each block represents 30 ms of audio data) less than calculated.
psb 4860 data sheet 68 2000-01-14 the psb 4860 offers the possibility to transfer the speech data via sci. to use this feature, the sci bit in register sdctl must be set. the speech decoder reads the speech data from register sddata. bit drq in register status indicates when new data is requested from sddata and the microcontroller must then write this data. when the microcontroller writes the data, the drq bit is cleared. table 37 shows the registers involved. table 37 speech decoder - data transfer via sci register # of bits name comment sdctl 1 sci speech data transfer via sci status 1 drq new data request sddata 16 data speech data
psb 4860 data sheet 69 2000-01-14 2.1.15 analog front end interface there are two identical interface channels to the analog frontend as shown in figure 36 . the interface is described in chapter 2.4.3 and must be connected to the double codec psb 4851. figure 36 analog front end interface - block diagram for each signal an amplifier is provided for level adjustment. the incoming signals can be passed through an optional high-pass (hp). this high-pass (f g =20 hz) is useful for blocking dc offsets and should be enabled by default. furthermore, up to three signals can be mixed in order to generate the outgoing signals (s 2 ,s 4 ). table 38 shows the associated registers. table 38 analog front end interface registers register # of bits name comment ifg1 16 ig1 gain for ig1 ifg2 16 ig2 gain for ig2 ifs1 1 hp high-pass for s 1 ifs1 5 i1 input signal 1 for ig2 ifs1 5 i2 input signal 2 for ig2 ifs1 5 i3 input signal 3 for ig2 ifg3 16 ig3 gain for ig3 ifg4 16 ig4 gain for ig4 ifs2 1 hp high-pass for s 3 ifs2 5 i1 input signal 1 for ig4 ifs2 5 i2 input signal 2 for ig4 ifs2 5 i3 input signal 3 for ig4 channel 2 s 1 channel 1 s 2 i 1 i 2 i 3 line out line in ig1 ig2 s 3 s 4 i 1 i 2 i 3 loudspeaker microphone ig4 hp ig3 hp
psb 4860 data sheet 70 2000-01-14 2.1.16 digital interface there are two almost identical interfaces at the digital side (i.e., the ssdi/iom ? -2 interface described in chapters 2.4.1 and 2.4.2 ). as shown in figure 37 , there are three channels available if the iom ? -2 interface is used while only channel 1 supports the ssdi mode figure 37 digital interface - block diagram each outgoing signal can be the sum of two signals with no attenuation and one signal with programmable attenuation (att). the attenuator can be used to generate an artificial side tone if the input (s 5 , s 7 , s 23 ) is connected to i 3 . each input can be passed through an optional high-pass (hp) to get rid of any dc part. channel 2 of the iom ? -2 can be split into two consecutive 8 bit channels with independent data streams (a-law or - law). it is therefore possible to use either two 16 bit linear channels, a 16 bit channel and an 8 bit channel, a 16 bit channel and two 8 bit channels or three 8 bit channels. the associated registers are shown in table 39 . table 39 digital interface registers register # of bits name comment ifs3 5 i1 input signal 1 for s 6 ifs3 5 i2 input signal 2 for s 6 ifs3 5 i3 input signal 3 for s 6 ifs3 1 hp high-pass for s 5 channel 2/3 (iom ? -2 interface) channel 1 (ssdi/iom ? -2 interface) s 7 /s 23 s 8/ s 24 i 1 i 2 i 3 att2/3 hp s 5 s 6 i 1 i 2 i 3 att1 hp
psb 4860 data sheet 71 2000-01-14 ifs4 5 i1 input signal 1 for s 8 ifs4 5 i2 input signal 2 for s 8 ifs4 5 i3 input signal 3 for s 8 ifs4 1 hp high-pass for s 7 ifs5 5 i1 input signal 1 for s 24 ifs5 5 i2 input signal 2 for s 24 ifs5 5 i3 input signal 3 for s 24 ifs4 1 hp high-pass for s 23 ifg5 8 att1 attenuation for input signal i3 (channel 1) ifg5 8 att2 attenuation for input signal i3 (channel 2) ifg6 8 att3 attenuation for input signal i3 (channel 3) table 39 digital interface registers register # of bits name comment
psb 4860 data sheet 72 2000-01-14 2.1.17 universal attenuator the contains an universal attenuator that can be connected to any signal (e.g. for side- tone gain in isdn applications). figure 38 universal attenuator - block diagram table 40 shows the associated register. table 40 universal attenuator registers register # of bits name comment ua 8 att attenuation for ua ua 5 i1 input signal for ua s 14 ua i 1
psb 4860 data sheet 73 2000-01-14 2.1.18 automatic gain control unit in addition to the universal attenuator with programmable but fixed gain the contains an amplifier with automatic gain control (agc). the agc is preceded by a signal summation point for two input signals. one of the input signals can be attenuated. figure 39 automatic gain control unit - block diagram furthermore the signal after the summation point is available. besides providing a general signal summation (s 16 not used) this signal is especially useful if the agc unit provides the input signal for the speech coder. in this case s 17 can be used as a reference signal for voice controlled recording as well as vox detection and gap coding. the operation of the agc is similar to agcx (agcr) of the speakerphone. the differences are as follows: no nois parameter enable/disable by bit en slightly different coefficient format the operation of the agc is similar to agcx (accr) of the speakerphone. the differences are as follows: no nois parameter separate enable/disable control slightly different coefficient format furthermore the agc contains a comparator that starts and stops the gain regulation. the signal after the summation point (s17) is used as input of a peak detector. for each maximum value, the peak detector catches the maximum and decays it with the time constant dec for decay until the next maximum is detected. the output signal of this peak detector is compared to a programmable limit lim. regulation takes only place when the filtered signal exceeds the limit. s 16 agc i 1 att i 2 s 17
psb 4860 data sheet 74 2000-01-14 table 41 shows the associated registers. table 41 automatic gain control registers register # of bits name comment agcctl 1 en enable agcctl 5 i1 input signal 1 for agc agcctl 5 i2 input signal 2 for agc agcatt 15 att attenuation for i 2 agc1 8 ag_init initial agc gain/attenuation agc1 8 com compare level rel. to max. pcm-value agc2 8 speedl change rate for lower levels agc2 8 speedh change rate for higher level agc3 7 ag_att attenuation range agc3 8 ag_gain gain range agc4 7 dec peak detector time constant agc4 8 lim comparator minimal signal level agc5 7 lp agc low pass time constant
psb 4860 data sheet 75 2000-01-14 2.1.19 equalizer the psb 4860 also provides an equalizer that can be inserted into any signal path. the main application for the equalizer is the correction to the frequency characteristics of the microphone, transducer or loudspeaker. the equalizer consists of an iir filter followed by an fir filter as shown in figure 40 . figure 40 equalizer - block diagram the coefficients a 1 -a 9 , b 2 -b 9 and c 1 belong to the iir filter, the coefficients d 1- d 17 and c 2 belong to the fir filter. table 42 shows the registers associated with the equalizer. table 42 equalizer registers register # of bits name comment fcfctl 1 en enable fcfctl 5 i input signal for equalizer fcfctl 6 adr filter coefficient address fcfcof 16 filter coefficient data z -1 z -1 z -1 a1 a2 a9 z -1 z -1 z -1 c1 b2 b9 z -1 z -1 z -1 d1 d2 d17 c2 s 18 i fir iir
psb 4860 data sheet 76 2000-01-14 due to the multitude of coefficients the psb 4860 uses an indirect addressing scheme for reading or writing an individual coefficient. the address of the coefficient is given by adr and the actual value is read or written to register fcfcof. in order to ease programming the psb 4860 automatically increments the address adr after each access to fcfcof. note: any access to an out-of-range address automatically resets fcfctl:adr.
psb 4860 data sheet 77 2000-01-14 2.1.20 peak detector the peak detector (figure 41 ) is usually not used in normal operation. it provides, however, an easy means to verify the minimum or maximum signal level of any signal s i within the . the peak detector stores either the maximum or the minimum signal value of the observed signal i 1 in the register pddata since the last read access to this register. therefore it is not only possible to determine the absolute level of the signal but it can also be checked whether a dc offset is present. this can be done by first scanning for the maximum and then for the minimum value. if the minimum value is not (approximately) the negated positive value then a dc offset is present. the peak detector should be disabled if not needed. figure 41 peak detector - block diagram the register pddata gives the maximum or minimum integer depending on the mode selected by bit mm. as an example it may be assumed that the detection of the maximum is selected. then with enabling the detector and with each read access to register pddata, pddata is set to the smallest possible value, which is the negative maximum integer. with each new maximum detected on signal i1, this maximum is provided by pddata. table 43 peak detector registers register # of bits name comment pdctl 1 en peak detector enable pdctl 1 mm minimum/maximum selection pdctl 5 i1 input signal selection pddata 16 min/max signal value since last read access peak sci i 1 detector
psb 4860 data sheet 78 2000-01-14
psb 4860 data sheet 79 2000-01-14 2.2 memory management memory management memory management - general this section describes the memory management provided by the . as figure 42 shows, three units can access the external memory. during recording, the speech coder can write compressed speech data into the external memory. for playback, the speech decoder reads compressed speech data from external memory. in addition, the microcontroller can directly access the memory by the sci interface. figure 42 memory management - data flow the memory is organized as a file system. the offers one directory for messages and one for voice prompts. these two directory have a similar structure. figure 43 illustrates the basic structure of the message directory. figure 43 memory management - structure of message directory the message directory contains 255 file descriptors, each describing one file. see the next section for details on files. speech decoder speech coder memory sci length (0-65535) user data (16 bits) file descriptor 1 file descriptor 255 file descriptor n file descriptor (r/w) directory rtc1 (16 bits) rtc2 (16 bits)
psb 4860 data sheet 80 2000-01-14 figure 44 illustrates the basic structure of the voice prompt directory. figure 44 memory management - structure of voice prompt directory the voice prompt directory contains 254 file descriptors. to each file descriptor a voice prompt file can be attached. the file with number 255 is a special file. if this file is selected, up to 2048 phrases can be used. the directories must be created after each power failure for volatile r/w-memory. all file descriptors are cleared (all words zero). for non-volatile memory, the directories have to be created only once. if the directories already exist, the memory just has to be activated after a reset. the file descriptors are not changed in this case. for detailed information on the structure of the directories, please refer to the appropriate application note. 2.2.1 file definition and access a file is a linear sequence of units and can be accessed in two modes: binary and audio. in binary mode, a unit is a word (16 bits). in audio mode, a unit is a variable number of words representing 30 ms of uncompressed speech. a file can contain at most 65535 units. figure 45 shows an audio file containing 100 audio units. the length of the message is therefore 3 s. figure 45 audio file organization - example file descriptor 1 file descriptor 254 file descriptor n directory phrase selected phrase 0 phrase 2048 ... hi jack, this is tom. please call me back tomorrow. 0 99 3 s
psb 4860 data sheet 81 2000-01-14 figure 46 shows a binary file of 11 words containing a phonebook (with only two entries). figure 46 binary file organization - example the file 255 in the voice prompt area offers a convenient handling of phrases. the large number of up to 2048 different phrases can be handled. each phrase can be of arbitrary length. in contrast to voice prompt files, phrases can be combined by the controller in any sequence without intermediate noise or gaps. figure 47 shows a phrase file containing a total of five phrases. figure 47 phrase file organization - example to access a file, the file must first be opened with the following information: 1. memory space (i.e., message or voice prompt directory) 2. file number 3. access mode these parameters remain effective until the next file open command is given. all other files are closed and cannot be accessed. the file with file number 0 does actually not exist. opening this file closes all existing files. the provides four registers for file access and three bits within the status register. table 44 shows these registers. table 44 memory management registers register # of bits comment fcmd 16 command to be executed fctl 16 access mode and file number fdata 16 data transfer and additional parameters fptr 16 (11) file pointer (phrase selector) status 16 busy, error and phrase queuing indication 544f 4d20 3535 3534 3330 004a 4143 4b20 5555 5538 3131 to 010 1 m 555430 jack 555811 one two you have messages left friday 01 4
psb 4860 data sheet 82 2000-01-14 file commands are written to the fcmd register. the busy bit in the status register is set within 150 s 1) (simultaneously with rdy). some commands require additional parameters which have to be written into the specified registers prior to the command. data transfer is done via the register fdata (both reading and writing). the status register contains two flags (table 45 ) to indicate if a file command is currently being executed (status:bsy) and if the last file command has terminated without error (status:err). a new command must not be written to fcmd while the last one is still running (status:bsy=1). the only commands that can be aborted are compress file and garbage collection. writing a valid command to fcmd also resets the error bit in the status register. table 46 shows the parameters defining the access mode and the access location. all parameters can only be written when no file command is currently active. new parameters become effective after the completion of a file open command. if another unit (e.g. speech coder) accesses the file, the file pointer is updated automatically. then, the controller can monitor the progress of recording or playing by reading the file pointer. 2.2.2 user data word the user data word is part of a file descriptor as illustrated in figures 43 and 44 . it offers an easy way to store some information on the file. 1) when the speakerphone is enabled it may take up to 250 s to set the bsy and the rdy bit. table 45 memory management status register # of bits name comment status 1 bsy file command or decoder/encoder still running status 1 err file command completed/aborted with error status 1 pqe phrase queue empty table 46 memory management parameters register # of bits name comment fctl 1 ms memory space (r/w or voice prompt) fctl 1 md access mode (audio or binary) fctl 1 ts write timestamp (file open only) fctl 1 ud write user data word fctl 8 fno file number (active file) fptr 16 file pointer or phrase selector
psb 4860 data sheet 83 2000-01-14 a user data word consists of 12 bits that can be read or written by the user, one bit (r) that is reserved for future use and three read-only bits (d,m,e) which indicate the status of a file. if d is set, the file is marked for deletion and should not be used any more. this bit is maintained by the for housekeeping. the m bit indicates the file type (audio/binary) while the e bit indicates an existing file. the e bit may be used after an activation to decide which files are actually valid and contain data. 2.2.3 high level memory management commands this section describes each of the high level memory management commands in detail. these commands are sufficient for normal operation of an answering machine. in addition, there are low level commands (section 2.2.4 ). these commands are only required for special tasks like in-system reprogramming of the voice prompt area. memory management - commands 2.2.3.1 initialize this command configures the memory. in case of flash, the message and the voice prompt directory are created. it is possible to reserve 4 kb of memory which is subsequently excluded from the standard file management. this reserved area can then be used for fast data backup (see emergency mode). the reserved 4kb memory block is called emergency block. in case of aram/dram, only the message directory is created since voice prompts are assumed to be kept in an additional rom. the can either create an empty directory from scratch or leave the first n files of an existing directory untouched while deleting the remaining files. this option is useful if due to an unexpected event (e.g. power loss during recording) some data are corrupted. in this case vital system information can still be recovered if it has been stored in the first files. furthermore, if bit mv indicates a voice prompt directory, the voice prompt memory is scanned for a valid directory. in any case, with the command initialize the checks the external memory configuration and delivers the size of usable memory in 1 kbyte blocks. 15 0 d m e r user definable table 47 initialize memory parameters register # of bits name comment fcmd 5 cmd initialize command code fcmd 1 in confirmation for initialization, must be set fcmd 1 reb reservation of 4 kb of memory
psb 4860 data sheet 84 2000-01-14 possible errors: no r/w memory found more than 55 bad blocks (flash and aram) voice prompt directory requested, but not detected wrong hardware connection note: this command should be given only once for flash devices. only for atmel flash devices w/o voice prompts, this command may be issued multiple times. 2.2.3.2 initialize message memory this command is only allowed if flash is used and assumes that initialize has been executed successfully. this command deletes all messages and generates a new message memory by using vital data of the voice prompt directory. the voice prompt area and therefore the prompt files and phrases are left untouched. for a successful execution, the voice prompts must have been prepared for this. if for example the download tools sprompt, aprompt, or tprompt are used they must have been started with the option -saverw. the command initialize message memory may help for recovery from a fatal system crash, which has damaged data in the flash memory. the emergency block (4 kb of memory that may have been reserved with the command initialize) keep untouched. fctl 8 fno 0: delete no file 1: delete all files n: delete starting with file n cctl 2 mt type of r/w memory (dram, flash) cctl 1 mq quality of r/w memory (audio, normal) cctl 1 mv scan for voice prompt directory cctl 2 sft serial flash type cctl 2 cdiv serial flash clock speed table 48 initialize memory results register # of bits name comment fdata 16 number of usable 1kbyte blocks in r/w memory table 47 initialize memory parameters register # of bits name comment
psb 4860 data sheet 85 2000-01-14 possible errors: file open note: this file command must be followed by the file command activate. 2.2.3.3 activate this command activates an existing directory, sets the external memory configuration and delivers the size of usable memory in 1 kbyte blocks. furthermore the voice prompt memory space is scanned for a valid directory. in case of aram/dram, the checks the consistency of the directory in the message memory space. it returns the first file that contains corrupted data (if any). if corrupted data is detected an initialization should be performed with the same file number as an input parameter. table 49 initialize memory parameters register # of bits name comment fcmd 5 cmd initialize command code fcmd 1 in confirmation for initialization, must be set cctl 2 mt type of r/w memory (dram, flash) cctl 1 mq quality of r/w memory (audio, normal) cctl 2 sft serial flash type cctl 2 cdiv serial flash clock speed table 50 activate memory parameters register # of bits name comment fcmd 5 cmd activate command code cctl 2 mt type of r/w memory (dram, flash) cctl 1 mq quality of r/w memory (audio, normal) cctl 1 mv voice prompt directory available cctl 2 sft serial flash type cctl 2 cdiv serial flash clock speed cctl 1 rd remap directory (see garbage collection)
psb 4860 data sheet 86 2000-01-14 possible error conditions: no memory connected no directory found device id wrong (flash only) corrupted files found (see fctl:fno) directory corrupted this command can have three types of results as shown in table 52 . note: if the flash is configured, the file command activate must be used for setting up the memory after power-up. 2.2.3.4 check voice prompt data integrity with this command, the psb 4860 calculates a crc value of voice prompt data and phrases contained in the voice prompt directory. the result can be read by the microcontroller in register fdata. this command can be used for verification of the downloaded phrases during production. table 51 activate memory results register # of bits name comment fdata 16 number of usable 1 kbyte blocks in r/w memory fctl 8 fno n: number of first corrupted file (dram/aram only) table 52 activate memory result interpretation result status: err fctl: fno comment no error 0 0 command successful, memory activated. soft error 1 n the first n-1 files are o.k. the memory is activated. hard error 1 1 the memory is not activated due to a hard error. table 53 read data parameters register # of bits name comment fcmd 5 cmd check voice prompt data integrity command code
psb 4860 data sheet 87 2000-01-14 possible error conditions: file open no activate performed no prompt directory existing 2.2.3.5 open file a specific file is opened for subsequent accesses with the specified access mode. opening a new file automatically closes the currently open file and clears the file pointer. opening file number 0 can be used to close all physical files. if the ts flag is set, the current contents of rtc1 and rtc2 is written to the appropriate fields of the file descriptor in order to provide a time stamp. if the ud flag is set, the contents of fdata is written to the user data word. note that for samsung and toshiba flash memory, bits within the user data word can only be changed from 0 to 1. possible error conditions: selected file marked for deletion, but not yet deleted by garbage collection new file selected, but memory full exceeds number of prompts (in voice prompt space only) wrong access mode selected for existing file has been recompressed partially table 54 read data results register # of bits name comment fdata 16 16 bit crc value table 55 open file parameters register # of bits name comment fcmd 5 cmd open command code fctl 1 ms memory space (r/w, voice prompt) fctl 1 md access mode (audio or binary) fctl 1 ts write time stamp fctl 1 ud write user data word fctl 8 fno file number fdata 12 user data word (if fctl:ud set)
psb 4860 data sheet 88 2000-01-14 note: in case of samsung and toshiba flash memory, existing ones in the entries rtc1/rtc2 of the file descriptor cannot be altered. therefore ts should be set only once during the lifetime of a file. 2.2.3.6 open next free file the next free file is opened for subsequent write accesses with the specified access mode. the search starts at the specified file number. if the ts flag is set, the current content of rtc1 and rtc2 is written to the appropriate fields of the file descriptor in order to provide a timestamp. if a free file has been found, the file is opened and the file number is returned in fctl:fno. otherwise an error is reported. the user data word can be written optionally. note that for flash memory, bits within the user data word can be only changed from 0 to 1. : possible error conditions: no unused file found memory full note: in case of samsung and toshiba flash memory existing ones cannot be altered. therefore ts should be set only once during the lifetime of a file. note: r/w-memory must be selected. otherwise the result is unpredictable. table 56 open next free file parameters register # of bits name comment fcmd 5 cmd open next free file command code fctl 1 md access mode (audio or binary) fctl 1 ts write timestamp fctl 8 fno starting point (>0) fctl 1 ud write user data word fdata 12 user data word (if fctl:ud set) table 57 open next free file results register # of bits name comment fctl 8 fno file number
psb 4860 data sheet 89 2000-01-14 2.2.3.7 seek the file pointer of the currently opened file is set to the position specified by fptr. if the current file is the phrase file the starts the speech decoder immediately after the seek is finished (the bit sdctl:en is set automatically). all other settings of the decoder remain unaffected. when the psb 4860 starts playing a phrase it automatically clears the fdata register and sets the pqe status bit. three audio blocks (90 ms) before the current phrase ends, the psb 4860 starts to check bit 15 of the fdata register. then, this bit must not be altered until the phrase ends. if this bit is set, the psb 4860 automatically appends the phrase denoted by the lower eleven bits of fdata to the current phrase without delay. once the new phrase has started the psb 4860 clears fdata and sets pqe again and the next phrase can be written by the controller. writing fdata automatically resets the pqe bit. the bsy bit of the status register is set immediately and reset when the last phrase has been finished. when the last phrase of a sentence is played, a phrase containing 120 ms silence should be appended. otherwise, the last 120ms of the last phrase are not played. possible error conditions: file pointer out of range phrase number out of range wrong cctl register content (e.g.: voice prompt directory specified but not present) 2.2.3.8 cut file all units starting with the unit addressed by the file pointer are removed from the file. if all units are deleted the file is marked for deletion (see user data word). however, the associated file descriptor and memory space are released only after a subsequent garbage collection. table 58 seek parameters register # of bits name comment fcmd 5 cmd seek command code fptr 16 (11) file pointer (phrase selector) fdata 16 next phrase (if bit 15 is set)
psb 4860 data sheet 90 2000-01-14 possible error conditions: file pointer out of range voice prompt memory selected 2.2.3.9 delete multiple files all files starting with the file number greater than or equal to the specified file number are marked for deletion. this command is intended to erase all messages with the exception of one or more outgoing messages. note that the associated file descriptors and memory space are released only after a subsequent garbage collection. possible error conditions: file open equal to 0 2.2.3.10 compress file an audio file can be recompressed using a lower bit rate than the current bit-rate of the file. this reduces the file size. the memory space is released after a subsequent garbage collection. this command can be aborted at any time and resumed later without loss of information. the target bit rate is selected by the speech encoder control register. the starting point of the recompression can be programmed as well. prior to this command all files must be closed. table 61 shows the parameters for this command. . table 59 cut file parameters register # of bits name comment fcmd 5 cmd cut command code fptr 16 position of first unit to be deleted (the first unit of a message has number 0) table 60 delete multiple files parameters register # of bits name comment fcmd 5 cmd cut command code fctl 8 fno first file number to be deleted table 61 compress file parameters register # of bits name comment fcmd 5 cmd compress command code scctl 2 q0, q1 target bit rate
psb 4860 data sheet 91 2000-01-14 possible error conditions: invalid another file currently open binary file selected note: after power fail during execution of this command, the file cannot be guaranteed to be a valid file. 2.2.3.11 memory status this command returns the number of available 1 kbyte blocks in r/w memory space. possible error conditions: file open 2.2.3.12 garbage collection this command initiates a garbage collection. until a garbage collection, files that are marked for deletion still occupy the associated file descriptor and memory space. after the garbage collection these file descriptors and the associated memory space are available again. this command can optionally remap the directory. in this mode the remaining file descriptors are remapped to form a contiguous block starting with file number 1. the original order is preserved. this command requires that all files are closed, i.e., file 0 is opened. independently of the selected directory only the read/write directory is used. the command can be aborted any time and resumed later on by fctl 8 fno file number fptr 16 start of recompression within file table 62 memory status parameters register # of bits name comment fcmd 5 cmd memory status code table 63 memory status results register # of bits name comment fdata 16 free number of free blocks table 61 compress file parameters register # of bits name comment
psb 4860 data sheet 92 2000-01-14 issuing the command again. note, that an aborted recompression command must be completed before a garbage collection can be performed. possible error conditions: file open recompression to be resumed 2.2.3.13 access file descriptor the file descriptors of the message memory can be accessed by two write and four read commands. the file descriptors of the voice prompt memory can be read but must not be written. the file is not affected by any of these commands. the two write commands are: write file descriptor - rtc1 / rtc2, and write file descriptor - user. with the command write file descriptor - rtc1 / rtc2, two values (rtc1 and rtc2) are written. this command can only be executed when no file is opened. with the command write file descriptor - user, only one value (user data) is written. this command can only be executed for a currently opened file. . there are four read commands, one for each of the file descriptor entries: user data, rtc1, rtc2, length. these commands can be executed for opened files or, when all files are closed, for the file with file number . table 64 garbage collection parameters register # of bits name comment fcmd 5 cmd garbage collection command code fcmd 1 rd remap directory table 65 write file descriptor parameters register # of bits name comment fcmd 5 cmd write access command code fdata 16 user data or rtc1 fptr 16 rtc2 fctl 16 fno file number table 66 read file descriptor parameters register # of bits name comment fcmd 5 cmd read access command code fctl 16 fno file number
psb 4860 data sheet 93 2000-01-14 possible error conditions: file open for command write file descriptor - rtc1 / rtc2 file not open for command write file descriptor - user note: in case of samsung and toshiba flash memory, bits already set to 1 cannot be altered. note: do not write with these commands to the voice prompt directory. 2.2.3.14 read data this command can be used in binary access mode only. a single word is read at the position given by the file pointer. the file pointer can be set by the seek command. the file pointer is advanced by one word automatically. possible error conditions: file pointer out of range audio file selected 2.2.3.15 write data this command can be used in binary access mode only. a single word is written at the position of the file pointer. the file pointer is advanced by one word automatically. note that for samsung and toshiba flash memories, only zeroes can be overwritten by ones. this restriction occurs only if an already used value within an existing file is to be overwritten. table 67 access file descriptor results register # of bits name comment fdata 16 content of selected entry table 68 read data parameters register # of bits name comment fcmd 5 cmd read data command code table 69 read data results register # of bits name comment fdata 16 data word
psb 4860 data sheet 94 2000-01-14 possible error conditions: file pointer out of range (for existing files only) voice prompt memory selected memory full audio file selected table 70 write data parameters register # of bits name comment fcmd 5 cmd access mode command code (including mode) fdata 16 data word
psb 4860 data sheet 95 2000-01-14 2.2.4 low level memory management commands these commands allow the direct access of any location (single word) of the external memory. additionally it is possible to erase any block in case of a samsung or toshiba flash device. these commands must not be used during normal operation as they may interfere with the file system. no file must be open when one of these commands is given. the primary use of these commands is the in-system programming of a flash device with voice prompts. please refer to the appropriate application note for usage of the following commands. 2.2.4.1 set address this command sets the 24 bit address pointer aptr. only the address bits a 8 -a 23 are set, the address bits a 0 -a 7 are automatically cleared. possible error conditions: file open 2.2.4.2 dma read this command initializes the read procedure. this command must be given before the read command can be issued. table 72 shows the parameter for this command. the overall procedure to read data is as follows. all accesses must be perfomed in handshake mode, i.e., the rdy must go active before the next step can be taken: 1. write address to register fdata. 2. write command set address to the command register fcmd. 3. initialize read with handshake by writing command dma read to fcmd. 4. start read of a word by transmitting 5a00 h via sci. 5. read data via sci similar to the data read access as described in chapter 2.4.4 . table 71 set address parameters register # of bits name comment fcmd 5 cmd set address command code fdata 16 adr address bits a 8 -a 23 of address pointer aptr table 72 dma read parameters register # of bits name comment fcmd 5 cmd dma read command code (initialization)
psb 4860 data sheet 96 2000-01-14 6. repeat 3) and 4) as often as necessary. the address is incremented automatically. neglect bsy bit for these transfers but consider the rdy bit (no interrupt is issued). 7. finish read access by transmitting 5f00 h via the sci possible error conditions: file open 2.2.4.3 dma write this command initializes the write procedure. this command must be given before the write command can be issued. table 73 shows the parameter for this command. the overall procedure to write data is as follows. all accesses must be perfomed in handshake mode, i.e., the rdy must go active before the next step can be taken:: 1. write address to register fdata. 2. write command set address to the command register fcmd. 3. initialize write with handshake by writing command dma write to fcmd. 4. write data via sci similar to the register write access as described in chapter 2.4.4 but use 4500 h as command word. 5. repeat 3) as often as necessary. the address is incremented automatically. neglect bsy bit for these transfers but consider the rdy bit (no interrupt is issued). 6. finish write access with a last register write access (after the last word has been written) with 4f00 h as command word. possible error conditions: file open note: if flash memory is connected the actual write is only performed when the last word within a page is written. until then the data is merely buffered in the flash device. please check the flash memory data sheets on page size. 2.2.4.4 block erase this command erases the physical block of a samsung of toshiba flash memory, which includes the address given by aptr. the actual amount of memory erased by this command depends on the block size of the flash device. table 74 shows the parameters for this command. table 73 dma write parameters register # of bits name comment fcmd 5 cmd dma write command code (initialization)
psb 4860 data sheet 97 2000-01-14 possible error conditions: file open aram/dram configured table 74 block erase parameters register # of bits name comment fcmd 5 cmd block erase command code
psb 4860 data sheet 98 2000-01-14 2.2.5 execution time the execution time of the file commands is determined by three factors: 1. memory configuration 2. memory state 3. individual characteristics of the memory devices therefore there is no general formula for an exact calculation of the execution time for file commands. for aram/dram the last item is not significant as the memory access timing is always fixed and no additional delay is incurred for erasing memory blocks. however, the amount of memory has significant impact on the initialization in case of aram and flash. for flash devices the particular location of a write access in combination with the internal organization of the memory device may result in a block erase and subsequent write accesses in order to copy data. in this case the individual erase and write timing of the attached devices also prolongs the execution time. table 75 gives an indication of the execution time for a typical memory configurations. the times for the samsung flash km29w040at are listed. table 75 execution times command max typical initialize < 3 s 0.5 s activate < 3 s 1 s open file /open next free file (no change to file or file descriptor) < 26 ms 1 ms open file /open next free file (change to file or file descriptor) < 160 ms - seek (within 4 mbit file) < 0.5 s - seek (within phrase file) < 1 ms - cut file < 5 ms 0.5 ms compress file #units * 30 ms #units * 30 ms access file descriptor < 10 ms 1 ms memory status < 10 ms 0.6 ms read/write data < 10 ms 125 us garbage collection < 3 s 1 s
psb 4860 data sheet 99 2000-01-14 2.2.6 special notes on file commands 1. no mmu commands must be inserted between opening a file and writing data to it, either by writing data to a binary file or by enabling the coder for audio files. therefore reading or writing the file descriptor is only allowed after all data writing has happened. 2. if an audio file has been opened for replay, a write file descriptor command must be followed by a seek command before the decoder can be enabled.
psb 4860 data sheet 100 2000-01-14
psb 4860 data sheet 101 2000-01-14 2.3 miscellaneous miscellaneous miscellaneous 2.3.1 real time clock the supplies a real time clock which maintains time with a resolution of one second and a range of up to one year. there are two registers which contain the current time and date (table 76 ). the real time clock maintains time during normal mode and power down mode only if the auxiliary oscillator osc is running and the rtc is enabled. note: writing out-of-range values to rtc1 and rtc2 results in undefined operation of the rtc 2.3.2 sps control register the two sps outputs (sps 0 , sps 1 ) can be used either as general purpose outputs, speakerphone status outputs, as extended address outputs for voice prompt eprom or as status register outputs. this is programmed with the bits mode. table 77 shows the associated register. when used as status register outputs, the status register bit at position pos appears at sps 0 and the bit at position pos+1 appears at sps 1 . this mode of operation can be used for debugging purposes or direct polling of status register bits. the rdy bit cannot be observed via sp0 or sp1. table 76 real time clock registers register # of bits name comment rtc1 6 sec seconds elapsed rtc1 6 min minutes elapsed rtc2 5 hr hours elapsed rtc2 11 day days elapsed table 77 sps register spsctl 1 sp0 output value of sps 0 spsctl 1 sp1 output value of sps 1 spsctl 3 mode mode of operation spsctl 4 pos position for status register window
psb 4860 data sheet 102 2000-01-14 2.3.3 reset and power down mode the can be in either reset mode, power down mode or active mode. during reset the clears the hardware configuration registers and stops both internal and external activity. the address lines ma 0 -ma 15 provide a weak low until they are actually used as address lines (strong outputs) or auxiliary port pins (i/o). in reset mode the hardware configuration registers can be read and written. with the first access to a read/write register the enters active mode. in this mode the main oscillator is running and normal operation takes place. by setting the power down bit (pd) the can be brought to power down mode. in power down mode the main oscillator is stopped and, depending on hwconfig2:ppm), the memory control lines are released (weak high). given that the auxiliary oscillator is still active and enabled (bit osc in register hwconfig0), then depending on the configuration (aram/dram, app), the may still generate external activity (e.g. refresh cycles). the enters active mode again upon an access to a read/ write register. figure 48 shows a state chart of the modes of the . figure 48 operation modes - state chart 2.3.4 interrupt the can generate an interrupt to inform the host of an update of the status register according to table 79 . an interrupt mask register (intm) can be used to disable or enable the interrupting capability of each bit of the status register except abt individually. table 78 power down bit register # of bits name comment cctl 1 pd power down mode reset active mode power down mode mode cctl.pd=1 r/w reg. access rst=1 rst=1 r/w reg. access
psb 4860 data sheet 103 2000-01-14 an interrupt is internally generated if any combination of these events occurs and the interrupt is not masked. this internal interrupt is cleared only when the host executes the data read access with interrupt acknowledge command. the internal interrupt is cleared when the first bit of the status register is output. if a new event occurs while the host reads the status register, the status register is updated after the current access table 79 interrupt source summary status (old) status (new) set by reset by rdy=0 rdy=1 command completed command issued cir=0 cir=1 new caller id byte requested cisdata written cis=0 cis=1 stop bits are sent cisdata written cia=0 cia=1 new caller id byte available cidctl0 read cd=0 cd=1 carrier detected carrier lost cd=1 cd=0 carrier lost carrier detected cpt/utd=0 cpt/utd=1 cpt or ut detected cpt or ut lost cpt/utd=1 cpt/utd=0 cpt or ut lost cpt or ut detected cng=0 cng=1 fax calling tone detected module disabled dtv=0 dtv=1 dtmf tone detected dtmf tone lost dtv=1 dtv=0 dtmf tone lost dtmf tone detected atv=0 atv=1 alert tone detected alert tone lost atv=1 atv=0 alert tone lost alert tone detected da=0 da=1 speech coder data in scdata data read by uc drq=0 drq=1 speech decoder requests data data written by uc bsy=1 bsy=0 file command completed new command issued sd=0 sd=1 speech activity detected speech activity lost sd=1 sd=0 speech activity lost speech activity detected gap=0 gap=1 gap start gap end gap=1 gap=0 gap end gap start vox=0 vox=1 vox detected voice detected vox=1 vox=0 voice detected vox detected pqe=0 pqe=1 phrase queue empty fdata written ipp=0 ipp=1 event at app input pin detected register dhold read
psb 4860 data sheet 104 2000-01-14 is terminated and a new interrupt is internally generated immediately after the access has ended. 2.3.5 abort if the cannot continue the current operations in progress (e.g. due to a transient loss of power) it stops operation and initializes all read/write registers to their reset state. after that it sets the abt bit of the status register and generates an interrupt. the discards all commands with the exception of a write command to the revision register while abt is set. only after the write command to the revision register (with any value) the abt bit is reset and a reinitialization can take place. 2.3.6 revision register the contains a revision register. this register is read only and does not influence operation in any way. a write to the revision register clears the abt bit of the status register but does not alter the content of the revision register. 2.3.7 hardware configuration the can be adapted to various external hardware configurations by four special registers: hwconfig0 to hwconfig3. these registers are usually only written once during initialization and must not be changed while the is in active mode. it is mandatory that the programmed configuration reflects the external hardware for proper operation. special care must be taken to avoid i/o conflicts or excess current by enabling inputs without an external driving source. table 80 can be used as a checklist. 2.3.8 frame synchronization the locks itself to either an externally supplied frame sync signal or generates the frame sync signal itself. this internal reference frame sync signal is called master frame sync (mfsc). table 81 shows how afeclk and mfsc are derived by the . the bits act and mfs are contained in the hardware configuration registers. the bit mfs controls whether the frame sync is taken from external or generated internally. the bit act enables the clock tracking and is explained in the sequel section. table 80 hardware configuration checklist register name value check hwconfig0 pfrdy 1 frdy must not float hwconfig0 osc 1 osc1/2 must be connected to a crystal hwconfig0 acs 1 clk must not float (tie low if no clock present) hwconfig1 mfs 1 fsc must not float (tie low if no clock present) hwconfig1 act 1 fsc must not float (tie low if no clock present)
psb 4860 data sheet 105 2000-01-14 2.3.9 clock tracking the can adjust afeclk and afefsc dynamically to a slightly varying fsc. this mode requires that both afefsc and fsc are nominally running at the same frequency (8 khz). it is enabled with the bit act in the hardware configuration registers. 2.3.10 afe clock source the can also derive its afeclk from an externally provided clock clk. this can be enabled with the bit acs in the hardware configuration registers. the external clock clk is expected to run at 13.824 mhz. table 81 frame synchronization selection act mfs afeclk mfsc application 0 0 xtal afefsc analog featurephone 0 1 - fsc isdn stand-alone 1 1 xtal fsc dect with psb 4851
psb 4860 data sheet 106 2000-01-14 2.3.11 restrictions and mutual dependencies of modules there are some restrictions concerning the modules that can be enabled at the same time. table 82 and 83 summarize these restrictions. a checked cell indicates that the two modules (defined by the row and the column of the cell) must not be enabled at the same time. examples: the line echo canceller (in 24 ms mode) cannot be enabled when the speech decoder is running at slow speed. if the dtmf detector is running, the compress file command (c) must not be executed. table 82 dependencies of modules - 1 speech encoder speech decoder line ec (24 ms) acoustic ec dtmf detector file command speech encoder x x x a speech decoder x x 1) 1) if speech decoder is running at slow speed x a line ec (24 ms) x x 1) x b acoustic ec x x x b dtmf detector c file command a a b b c table 83 dependencies of modules - 2 caller id sender caller id decoder alert tone det cpt detector utd detector file command cid sender x c cid decoder x x 1) 1) if cidctl0:cm is set. c 1) at detector x 1) cpt detector x upt detector x file command c c 1)
psb 4860 data sheet 107 2000-01-14 there are three classes of file commands denoted by the letters a, b and c. table 84 shows the definitions of these classes: a further restriction occurs due to the resource costs of the simultaneously applied modules. each module currently in use takes up some resources. the percentage a module needs from the totally available resources is listed in table 85 . the sum of resources all applied modules must never exceed 100. the amounts listed on table 85 are valid for 31.104 mhz operating frequency. if the psb 4860 runs at a higher or lower frequency, the resource costs decrease or increase accordingly. thus, it may be necessary to restrict the length of the fir filter of the echo cancellation unit if several other units are operating at the same time. table 84 file command classes class description a all commands b background commands (activate, recompress, garbage collection, initialize, initialize message memory, delete multiple files) and open commands (open, open next free file) c recompress command table 85 module weights module weight comment example 1 example 2 equalizer 2.8 x x cpt detector 5.6 caller id decoder 4.2 cm = 0 x caller id decoder 10.9 cm = 1 cng detector 2.6 dtmf generator 2.2 x echo cancellation 52.7 127 taps (16 ms) echo cancellation 63.1 255 taps (32 ms) x echo cancellation 73.6 383 taps (48 ms) echo cancellation 84.0 511 taps (64 ms) x line echo cancellation 12.8 normal mode line echo cancellation 25.5 extended mode line echo cancellation 14.3 superior mode x universal attenuator 0.2
psb 4860 data sheet 108 2000-01-14 example: for an analog phone echo cancellation, dtmf tone generation, caller id reception, and line echo cancellation are necessary. the system uses the psb 4851 and the equalizer to linearize the loudspeaker. in this case the sum of all weights without echo cancellation is 34.4. therefore 255 taps can be used for a total of 97.5. in an isdn phone echo cancellation, channel 1 of the digital interface, the analog interface with clock tracking and the equalizer shall be enabled at the same time. in this application the sum of all weights without echo cancellation is 16.0. therefore 511 taps can be used for a total of 99.8. digital interface 1.7 channel 1 or ssdi x digital interface 1.7 channel 2 digital interface 1.7 channel 3 analog interface 2.5 x x clock tracking 0.6 x miscellaneous 8.4 always active x x alert tone detector 2.8 off hook universal tone detector 3.5 on hook dtmf detector 5.2 caller id sender 4.3 speech coder 62.5 + agc 2.6 + vox detection 0.8 + gap coding 2.6 speech decoder 31.8 table 85 module weights module weight comment example 1 example 2
psb 4860 data sheet 109 2000-01-14 2.3.12 emergency mode this mode is intended for a fast backup of controller data into non-volatile memory (flash memory) connected to the psb 4860. in short, with this mode a maximum of 2048 bytes can be transferred with less than 20 ms overhead additional to the time needed by the flash itself for writing data. this mode can be entered from normal mode only and returns to power-down mode when finished. when this mode is entered the psb 4860 disables all modules immediately. only aram/dram refresh, the auxiliary parallel port and the sci interface remain active. if a file was recorded at the time the emergency mode has been entered, the file may get truncated or deleted completely depending on the memory configuration: atmel entering emergency mode immediately w ill loose the currently recorded file. the associated memory will be recovered upon the next activate command. samsung the file can be closed immediately and emergency mode can be entered immediately. the currently recorded file will be saved. toshiba the file can be closed immediately and emergency mode can be entered immediately. the currently recorded file will be saved. however, the maximum block erase time of the flash device must be taken into account (worst case). however, all other files will remain intact. in addition, no memory space will get lost due to the file truncation. once the emergency mode has been entered, the psb 4860 expects up to 2048 bytes of data. the data is transferred as a contiguous block from the controller to the psb 4860. with each access (48 sclk cycles) three bytes can be transferred. the controller does not have to wait for a confirmation from the psb 4860 for this block transfer. therefore, at an sclk frequency of 2 mhz the maximal block size of 2048 byte can be transferred in approximately 18 ms. once the data has been transferred to the psb 4860 the data is written to a prepared page in the flash device. the psb 4860 goes into powerdown mode as soon as possible (after the last necessary write access to the flash device). the emergency mode can also be used for fast file close. then the command that indicates the end of the transmission has to be issued instead of writing the first byte. in this case no emergency block of the memory needs to be reserved with the command initialize. the psb 4860 must be activated again before it can resume normal operation. in order to use this mode the psb 4860 must be told to set aside some memory during initialization as described in section 2.2.3.1. this reserved memory is then excluded from the normal access (messages and voice prompts) and thus provides an already erased (ready to write) location for the backup of the block data.
psb 4860 data sheet 110 2000-01-14 procedure: 1. preparation if a file command is currently running (except record, playback or phrase playback) then the file command must be aborted by setting the ica bit of register fcmd. the file command will be aborted within 15 ms (all memories except toshiba) or 110 ms (worst case toshiba). this step is completed when the bsy bit of the status register is reset. 2. entering emergency mode emergency mode is entered by setting bit em of the cctl register. this step is completed when the rdy bit of the status register is set again. 3. data transmission from controller to the controller can transfer any amount of data in steps of three bytes each from three bytes to 2046 bytes. this data transfer does not use any handshake mechanism. at a sclk frequency of 2 mhz, the controller can issue data transfer commands at full speed. there are two commands available (table 86 ): the transfer emergency data command is a special type of a write register command (table 95 and figure 61 ). each transfer emergency data command transfers three bytes of data to the . the first byte is already encoded in the command word itself while the next two bytes are transmitted in the data word. once all data bytes have been transferred, a write to memory command with a dummy data word must be given. this has to be done even if no byte was and neither needs to be transferred. 4. data transmission from to memory after receiving the write to memory command the automatically starts to transfer all received data to the reserved block in external memory. this step is completed when the pd bit of register hwconfig0 is set (i.e. the is in power down mode). 5. recovery data recovery from the reserved block can be done after the next activation by the low level memory management commands. table 86 command words for emergency mode data transfer 1514131211109876543210 transfer emergency data 0 1 0 0 0 1 0 1 byte 1 write to memory 01001 11100000000
psb 4860 data sheet 111 2000-01-14 2.4 interfaces interfaces interfaces this section describes the interfaces of the . the supports both an iom ? -2 interface with single and double clock mode and a strobed serial data interface (ssdi). however, these two interfaces cannot be used simultaneously as they share some pins. both interfaces are for data transfer only and cannot be used for programming the . the is slave and the frame synchronization as well as the data clock are inputs. table 87 lists the features of the two alternative interfaces. 2.4.1 iom ? -2 interface the data stream is partitioned into packets called frames. each frame is divided into a programmable number of timeslots. each timeslot is used to transfer 8 bits. figure 49 shows a commonly used terminal mode (three channels ch 0 , ch 1 and ch 2 with four timeslots each). the first timeslot (in figure 49 : b1) is denoted by number 0, the second one (b2) by 1 and so on. figure 49 iom ? -2 interface - frame structure the signal fsc is used to indicate the start of a frame. figure 50 shows as an example two valid fsc-signals (fsc, fsc * ) which both indicate the same clock cycle as the first clock cycle of a new frame (t 1 ). table 87 ssdi vs. iom ? -2 interface iom ? -2 ssdi signals 4 6 channels (bidirectional) 3 1 code linear pcm (16 bit), a-law, -law (8 bit) linear pcm (16 bit) synchronization within frame by timeslot (programmable) by signal (dxst, drst) b1 m0 b2 fsc dd/du ch 0 ch 1 ch 2 125 s ci0 ic1 m1 ic2 ci1
psb 4860 data sheet 112 2000-01-14 note: any timeslot (including m0, ci0, ...) can be used for data transfer. however, programming is not supported via the monitor channels. figure 50 iom ? -2 interface - frame start the supports both single clock mode and double clock mode. in single clock mode, the bit rate is equal to the clock rate. bits are shifted out with the rising edge of dcl and sampled at the falling edge. in double clock mode, the clock runs at twice the bit rate. therefore for each bit there are two clock cycles. bits are shifted out with the rising edge of the first clock cycle and sampled with the falling edge of the second clock cycle. figure 51 shows the timing for single clock mode and figure 52 shows the timing for double clock mode. figure 51 iom ? -2 interface - single clock mode dcl fsc fsc * t 1 t 2 dcl t 1 t 2 dd/dr du/dx bit 0bit 1bit 2 bit 0bit 1bit 2
psb 4860 data sheet 113 2000-01-14 figure 52 iom ? -2 interface - double clock mode the supports up to three channels simultaneously for data transfer. if only two channels are used, then both the coding (pcm a-law, pcm -law or linear) and the data direction (dd/du assignment for transmit/receive) can be programmed individually. the psb 4860 supports a third channel by simply splitting the second 16 bit channel into two 8 bit channels. therefore the following restrictions occur for channel 2 and 3 in this case: 1. channel two as well as three must use pcm coding (both either a-law or -law) 2. channel three is on an even timeslot 3. channel two is on the following odd timeslot to enabled the channel splitting, bit sdchn2:cs must be set and bit sdchn2:pcm cleared. the selection of bit sdchn2:pcd holds then for both channels. table 88 shows the registers used for configuration of the iom ? -2 interface. table 88 iom ? -2 interface registers register # of bits name comment sdconf 1 en interface enable sdconf 1 dcl selection of clock mode sdconf 6 nts number of timeslots within frame sdchn1 1 en channel 1 enable sdchn1 6 ts first timeslot (channel 1) sdchn1 1 dd data direction (channel 1) sdchn1 1 pcm 8 bit code or 16 bit linear pcm (channel 1) sdchn1 1 pcd 8 bit code (a-law or -law, channel 1) sdchn2 1 en channel 2 enable sdchn2 1 cs channel 2 split (into two contiguous 8 bit channels) sdchn2 6 ts first timeslot (channel 2) dcl t 1 dd/dr du/dx bit 0bit 1bit 2 bit 0 bit 1 t 2 t 3 t 4 t 5
psb 4860 data sheet 114 2000-01-14 in a-law or -law mode, only 8 bits are transferred and therefore only one timeslot is needed for a channel. in linear mode, 16 bits are needed for a single channel. in this mode, two consecutive timeslots are used for data transfer. bits 8 to 15 are transferred within the first timeslot and bits 0 to 7 are transferred within the next timeslot. the first timeslot must have an even number. figure 53 shows as an example a single channel in linear mode occupying timeslots 2 and 3. each frame consists of six timeslots and single clock mode is used. figure 53 iom ? -2 interface - channel structure at this rate the data is shifted out with the rising edge of the clock and sampled at the falling edge. the data clock runs at 384 khz (six timeslots with 8 bit each within 125 s). sdchn2 1 dd data direction (channel 2) sdchn2 1 pcm 8 bit code or 16 bit linear pcm (channel 2) sdchn2 1 pcd 8 bit code (a-law or -law, channel 2) table 88 iom ? -2 interface registers register # of bits name comment fsc dd/du d 15 d 10 d 11 d 12 d 13 d 14 d 9 d 8 d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 3
psb 4860 data sheet 115 2000-01-14 2.4.2 ssdi interface the ssdi interface is intended for seamless connection to low-cost burst mode controllers (e.g. pmb 4725) and supports a single channel in each direction. the data stream is partitioned into frames. within each frame, one 16 bit value can be sent and received by the . the start of a frame is indicated by the rising edge of fsc. data is always sampled at the falling edge of dcl and shifted out with the rising edge of dcl. the ssdi transmitter and receiver are operating independently of each other except that both use the same fsc and dcl signal. 2.4.2.1 ssdi interface - transmitter the indicates outgoing data (on signal dx) by activating dxst for 16 clocks. the signal dxst is activated with the same rising edge of dcl that is used to send the first bit (bit 15) of the data. dxst is deactivated with the first rising edge of dcl after the last bit has been transferred. the drives the signal dx only when dxst is activated. figure 54 shows the timing for the transmitter. figure 54 ssdi interface - transmitter timing 2.4.2.2 ssdi interface - receiver valid data is indicated by an active drst pulse. each drst pulse must last for exactly 16 dcl clocks. as there may be more than one drst pulses within a single frame the can be programmed to listen to the n-th pulse with n ranging from 1 to 16. in order to detect the first pulse properly, drst must not be active at the rising edge of fsc. in figure 55 the is listening to the third drst pulse (n=3). fsc 125 s dxst dcl du/dx bit 15 bit 14 bit 1 bit 0
psb 4860 data sheet 116 2000-01-14 figure 55 ssdi interface - active pulse selection figure 56 shows the timing for the ssdi receiver. figure 56 ssdi interface - receiver timing table 89 shows the registers used for configuration of the ssdi interface. table 89 ssdi interface register register # of bits name comment sdchn1 4 nas number of the active drst strobe fsc drst active pulse (n=3) fsc 125 s drst dcl dd/dr bit 15 bit 14 bit 1 bit 0
psb 4860 data sheet 117 2000-01-14 2.4.3 analog front end interface the uses a four wire interface similar to the iom ? -2 interface to exchange information with the analog front end (psb 4851). the main difference is that all timeslots and the channel assignments are fixed as shown in figure 57 . the is master of this interface and provides afefs as well as afeclk. . figure 57 analog front end interface - frame structure voice data is transferred in 16 bit linear coding in two bidirectional channels c 1 and c 2 . an auxiliary channel c 3 is used to transfer the current setting of the loudspeaker amplifier als to the . the remaining bits are fixed to zero. in the other direction c 3 transfers an override value for als from the to the psb 4851. an additional override bit ov determines if the currently transmitted value should override the aoar:lsc 1) setting. the aoar:lsc setting is not affected by c 3 :als override. table 90 shows the source control of the gain for the als amplifier. furthermore the afe interface can be enabled or disabled according to table 91 . 1) see specification of psb 4851, automatically set by the in loudhearing mode. table 90 control of als amplifier aopr:ovre c 3 :ov gain of als amplifier 0 - aoar:lsc 1 0 aoar:lsc 11c 3 :als table 91 analog front end interface register register # of bits name comment afectl 1 en interface enable channel c 1 channel c 3 channel c 2 afefs afedd 125 s als afedu unused 000ov 16 bit 16 bit 8 bit
psb 4860 data sheet 118 2000-01-14 figure 58 analog front end interface - frame start figure 58 shows the synchronization of a frame by afefs. the first clock of a new frame (t 1 ) is indicated by afefs switching from low to high before the falling edge of t 1 . afefs may remain high during subsequent cycles up to t 32 . figure 59 analog front end interface - data transfer the data is shifted out with the rising edge of afeclk and sampled at the fa lling edge of afeclk (figure 59 ). if aopr:ovre is not set, the channel c 3 is not used by the psb 4851. all values (c 1 , c 2 , c 3 :als) are transferred msb first. the data clock (afeclk) rate is fixed at 6.912 mhz. table 92 shows the clock cycles used for the three channels. table 92 analog front end interface clock cycles clock cycles afedd (driven by ) afedu (driven by psb 4851) t 1 -t 16 c 1 data c 1 data t 17 -t 32 c 2 data c 2 data t 33 -t 40 c 3 data c 3 data t 41 -t 864 0tristate afeclk afefs t 1 t 2 afeclk t 1 t 2 afedd afedu bit 0bit 1bit 2 bit 0bit 1bit 2
psb 4860 data sheet 119 2000-01-14 2.4.4 serial control interface the serial control interface (sci) uses four lines: sdr, sdx, sclk and cs . data is transferred by the lines sdr and sdx at the rate given by sclk. the falling edge of cs indicates the beginning of an access. data is sampled by the at the rising edge of sclk and shifted out at the falling edge of sclk. each access must be terminated by a rising edge of cs . the accesses to the can be divided into four classes: 1. configuration read/write 2. register read/write 3. status/data read 4. status/data read with interrupt acknowledge if the is in power down mode, a read access to the status register does not deliver valid data with the exception of the rdy bit (rdy=0). after the status has been read the access can be either terminated or extended to read data from the . a register read/write access can only be performed when the is ready. the rdy bit in the status register provides this information. any access to the starts with the transfer of 16 bits to the over line sdr. this first word specifies the access class, access type (read or write) and, if necessary, the register accessed. two access types terminate after the first word: configuration register write and register read. if the configuration register is written, the first word also includes the data and the access is terminated. after an access register read, an access of type data read is necessary to obtain the register data. however, the data is valid only when status:rdy=1. with a second word, all accesses beside configuration register write and register read deliver the status register from the via line sdx. after the second word, the access status register read terminates while all other accesses transfer data with a third word and terminate then. figures 60 to 63 show the timing diagrams for the different access classes and types to the .
psb 4860 data sheet 120 2000-01-14 figure 60 status register read access figure 61 data read access cs sclk sdr c 15 c 14 c 1 c 0 s 15 s 14 s 1 s 0 sdx c 15 ,..,c 0 : s 15 ,..,s 0 : command word for status register read : status register : int cs sclk sdr c 15 c 14 c 1 c 0 s 15 s 14 s 1 s 0 sdx c 15 ,..,c 0 : s 15 ,..,s 0 : command word for data read : status register : d 15 d 14 d 1 d 0 d 15 ,..,d 0 : data to be read :
psb 4860 data sheet 121 2000-01-14 figure 62 register write access figure 63 configuration register read access configuration registers at even adresses use bit positions d 7 -d 0 while configuration registers at odd adresses use bit positions d 15 -d 8 . cs sclk sdr c 15 c 14 c 1 c 0 s 15 s 14 s 1 s 0 sdx c 15 ,..,c 0 : s 15 ,..,s 0 : command word for register write : status register : d 15 d 14 d 1 d 0 d 15 ,..,d 0 : data to be written : cs sclk sdr c 15 c 14 c 1 c 0 sdx c 15 ,..,c 0 : s 15 ,..,s 0 : command word for configuration register read : status register : d 15 ,..,d 0 : data to be read : s 15 s 14 s 1 s 0 d 15 d 14 d 1 d 0
psb 4860 data sheet 122 2000-01-14 figure 64 configuration register write access or register read command for all commands the external signal int is deactivated as long as the chip is selected (cs is low). for a detailed discussion about the behavior of the interrupt signal please see section 2.3.4 . table 93 shows the formats of the different command words. all other command words are reserved. note that interrupts are only acknowledged (cleared) if the command read status/data with interrupt acknowledge is issued. in case of a configuration register write, w determines what configuration register is to be written (table 94 ): table 93 command words for register access 1514131211109876543210 read status register or data read access (interrupt acknowledge) 0011000000000000 read status register or data read access 1) 1) does not acknowledge interrupt. 1001000000000000 read register 1) 0101 reg write register 1) 0100 reg read configuration reg.011100r000000000 write configuration reg. 0 1 1 0 0 0 w data table 94 address field w for configuration register write 9 8 register 0 0 hwconfig 0 0 1 hwconfig 1 1 0 hwconfig 2 1 1 hwconfig 3 cs sclk sdr c 15 c 14 c 1 c 0 c 15 ,..,c 0 : command word for configuration register write : or register read :
psb 4860 data sheet 123 2000-01-14 in case of a configuration register read, r determines what pair of configuration registers is to be read (table 95 ): note: reading any register except the status register or a hardware configuration register requires at least two accesses. the first access is a register read command (figure 64 ). with this access the register address is transferred to the . after that access data read accesses (figure 61 ) must be executed. the first data read access with status:rdy=1 delivers the value of the register. table 95 address field r for configuration register read 9 register pair 0 hwconfig 0 / hwconfig 1 1 hwconfig 2 / hwconfig 3
psb 4860 data sheet 124 2000-01-14
psb 4860 data sheet 125 2000-01-14 2.4.5 memory interface the supports either flash memory or aram/dram as external memory for storing messages. if aram/dram is used, an eprom can be added optionally to support read- only messages (e.g. voice prompts). note: although the memory accesses are performed by the , the specification of the used memory (e.g. number of re-write cycles in case of flash) has to be regarded by the controller. table 96 summarizes the different configurations supported. if aram/dram is used, the total amount of memory must be a power of two. if more than one memory device is used, the memory devices must be of the same type. for flash devices, voice prompts do not need to be programmed via the psb 4860. they can also directly be programmed by any other circuitry into the flash. this is supported table 96 supported memory configurations mbit type bank 0 (d 0 -d 3 ) bank 1 (d 4 -d 7 )comment 4 aram/dram 1mx4 - 4 aram/dram 4mx1 - d 0 only 4 aram/dram 512kx8 8 aram/dram 1mx4 1mx4 16 aram/dram 4mx4 - 2k or 4k refresh 16 aram/dram 16mx1 - d 0 only 16 aram/dram 2mx8 2k refresh 32 aram/dram 4mx4 4mx4 2k or 4k refresh 32 aram/dram 2x2mx8 2k refresh 64 aram/dram 16mx4 - 4k or 8k refresh 64 aram/dram 8mx8 4k or 8k refresh 128 aram/dram 16mx4 16mx4 4k or 8k refresh 4-128 flash 512kx8 km29n040 8-128 flash 1mx8 km29w8000 16-128 flash 2mx8 km29n16000 4-16 flash 4mx1 tc58a040 4-16 flash 4mx1 at45db041 8-32 flash 8mx1 at45db081 16-64 flash 16mx1 at45db161
psb 4860 data sheet 126 2000-01-14 by the psb 4860 insofar as the control lines are released during reset and (optionally) power down. instead of actively driving the lines fcs , foe , fwe , fcle and ale these lines are pulled high by a weak pullup during reset and (optionally) power down.
psb 4860 data sheet 127 2000-01-14 2.4.5.1 aram/dram interface the supports up to two banks of memory which may be 4 bit or 8 bit wide (figure 65 ). if both banks are used, each one is connected identically with exception of the data lines d 0 - d 7 . these must be connected as described by table 96 . the pin frdy must be tied high. figure 65 aram/dram interface - connection diagram the also supports different internal organizations of aram/dram chips. table 97 shows the necessary connections on the address bus. table 97 address line usage (aram/dram mode) aram/dram cs9 1) ma 0 -ma 8 ma 9 ma 10 ma 11 ma 12 ma 13 256k x4 1 a 0 -a 8 512k x8 1 a 0 -a 8 a 9 ma 0 -ma 1 5 md 0 -md 3 ras cas 0 w a 0 -a 12 d 0 -d 3 ras cas w oe a 0 -a 12 d 0 -d 7 ras cas w oe single 4 bit bank single 8 bit bank ma 0 -ma 1 5 md 0 -md 7 ras cas 0 w ma 0 -ma 1 5 md 0 ras cas 0 w a 0 -a 12 d 0 ras cas w oe single 1 bit bank psb 4860 psb 4860 psb 4860
psb 4860 data sheet 128 2000-01-14 the timing of the aram/dram interface is shown in figures 66 to 68 . the timing is derived from the internal memory clock mclk which runs at a quarter of the system clock. figure 66 aram/dram interface - read cycle timing 1m x4 0 a 0 -a 8 a 9 4m x4 (2k refresh) 0 a 0 -a 8 a 9 a 10 4m x4 (4k refresh) 0 a 0 -a 8 a 9 a 10 a 11 2m x8 0 a 0 -a 8 a 9 a 10 16m x4 (4k refresh) 0 a 0 -a 8 a 9 a 10 a 11 16m x4 (8k refresh) 0 a 0 -a 8 a 9 a 10 a 11 a 12 8m x8 (4k refresh) 0 a 0 -a 8 a 9 a 10 a 11 8m x8 (8k refresh) 0 a 0 -a 8 a 9 a 10 a 11 a 12 1) see chip control register cctl table 97 address line usage (aram/dram mode) mclk ma 0 -ma 13 md 0 -md 7 cas 0 ,cas 1 ras row addr. col. addr.
psb 4860 data sheet 129 2000-01-14 figure 67 aram/dram interface - write cycle timing figure 68 aram/dram interface - refresh cycle timing the ensures that ras remains inactive for at least one mclk-cycle between successive accesses. the frequency at which refresh cycles are performed is shown in table 98 . table 98 refresh frequency selection refresh frequency comment 64 khz memory access (e.g. recording) in progress 8, 16, 32 or 64 khz 1) 1) as programmed by hwconfig2:rsel no memory access in progress or power-down mclk ma 0 -ma 13 md 0 -md 7 cas 0 ,cas 1 ras row addr. col. addr. w data out mclk cas 0 ,cas 1 ras
psb 4860 data sheet 130 2000-01-14 2.4.5.2 eprom interface the supports an eprom in parallel with aram/dram. this interface is always 8 bits wide and supports a maximum of 256 kbytes. figure 69 shows a connection diagram and figure 70 shows the timing. this interface supports read cycles only. figure 69 eprom interface - connection diagram figure 70 eprom interface - read cycle timing note: in order to access more than 64 kbytes the pins sps 0 and sps 1 can be programmed to provide the address lines a 16 and a 17 . in this mode a 16 and a 17 remain stable during the whole read cycle. see the register spsctl for programming information. ma 0 -ma 1 5 md 0 -md 7 vprd a 0 -a 15 d 0 -d 7 ce oe a 16 a 17 sps 1 sps 0 vprd md 0 -md 7 mclk* ma 0 -ma 15
psb 4860 data sheet 131 2000-01-14 2.4.5.3 parallel flash memory interface the has special support for km29n040, km29w8000 and km29n16000 or equivalent devices. figure 71 shows the connection diagram for a single device. figure 71 parallel flash memory interface - connection diagram no external components are required if up to four devices km29n040 are used. the select signals fcs 0 -fcs 3 can directly be used to access up to four devices. the determines the number of connected devices automatically. table 99 shows the signals on the ma-lines during a device access. furthermore, none of the parallel flashs needs all address liness. therefore, the upper address lines can additionally be used to access multiple devices. then, they have to be decoded by an external decoder. table 99 address line usage (samsung mode) ma 11 ma 10 ma 9 ma 8 ma 7 ma 6 ma 5 ma 4 ma 3 ma 2 ma 1 ma 0 fcs 3 fcs 2 fcs 1 fcs 0 a 23 a 22 a 21 a 20 a 19 a 18 a 17 a 16 d 0 -d 7 ce re we cle md 0 -md 7 fcs foe fwr fcle ale ale +5v r/b frdy wp
psb 4860 data sheet 132 2000-01-14 figure 72 shows an application with three km29n040 devices. figure 72 parallel flash memory interface - multiple devices an access to the flash memory can consist of several partial access cycles where only the timing of the partial access cycles is defined but not the time between two consecutive partial access cycles. the performs three types of partial access cycles: 1. command write 2. address write 3. data read/write table 100 shows the supported accesses and the corresponding partial access cycles. table 100 flash memory command summary access command write address write 1 address write 2 address write 3 # of data read/write command write reset ff - - - - - status read 70 - - - 1 - block erase 60 a 8 -a 15 a 16 -a 23 --d0 read 00 a 0 -a 7 a 8 -a 15 a 16 -a 23 1-32 - write 80 a 0 -a7 a 8 -a 15 a 16 -a 23 1-32 10 d 0 -d 7 ce re we cle md 0 -md 7 foe fwr frdy ale ale +5v r/b fcle wp d 0 -d 7 ce re we cle ale r/b wp ma 8 ma 9 ma 10 d 0 -d 7 ce re we cle ale r/b wp
psb 4860 data sheet 133 2000-01-14 the timing for the partial access cycles is shown in figures 73 to 74 . note that both fcs and ma 0 -ma 15 remain stable between the first and the last partial access of a device access. figure 73 parallel flash memory interface - command write figure 74 parallel flash memory interface - address write as there is no access that starts or stops with an address write cycle (figure 74 ) fcs is already low at the start of this cycle and also remains low. mclk* ma 0 -ma 11 md 0 -md 7 fwr fcs fcle data out mclk* md 0 -md 7 fwr ale data out address latch cycle t 0 t 1 t 2 t 3
psb 4860 data sheet 134 2000-01-14 figure 75 parallel flash memory interface - data write as there is no access that starts or stops with a data write cycle (figure 75 ) fcs is already low at the start of this cycle and also remains low. figure 76 parallel flash memory interface - data read if the device access ends with a read cycle, the fcs -signals go inactive after t 3 of the last read cycle. the data is latched at the rising edge of foe . mclk* md 0 -md 7 fwr data out write cycle t 0 t 1 t 2 t 3 mclk* md 0 -md 7 foe data in read cycle t 0 t 1 t 2 t 3
psb 4860 data sheet 135 2000-01-14 2.4.5.4 serial flash memory interface the psb 4860 can be connected to up to four identical devices. it determines the number of connected devices automatically. the controller must provide the information on the type of the devices (toshiba or atmel). table 101 lists the used pins. the following figures show the connection diagrams for various configurations. figure 77 serial flash - connection to single tc 58 a 040 f figure 78 serial flash - connection to single at 45 db 041 table 101 pin functions for serial flash interface pin nr. name comment 42 md 0 /sclk clock output for serial interface 43 md 1 /sdi data in from flash device 44 md 2 /sdo data out from psb 4860 46 md 4 /cs 0 chip select for first device 47 md 5 /cs 1 chip select for second device 50 md 6 /cs 2 chip select for third device 51 md 7 /cs 3 chip select for fourth device md 0 /sclk md 2 /sdo md 1 /sdi md 4 /cs 0 sk do tc 58 a 040 f di cs psb 4860 md 0 /sclk md 2 /sdo md 1 /sdi md 4 /cs 0 sck so at 45 db 041 si cs psb 4860 frdy rdy/busy
psb 4860 data sheet 136 2000-01-14 in each case multiple devices can be connected by sharing the lines md 0 /sclk, md 1 / sdi and md 2 /sdo as shown in figure 79 . figure 79 serial flash - connection to multiple tc 58 a 040 f table 102 shows the registers associated with the memory interface. table 102 memory interface registers register # of bits name comment hwconfig0 1 pfrdy enable internal pull-up resistance at frdy input hwconfig2 2 rsel refresh cycle selection hwconfig3 1 sfi serial flash selection cctl 2 cdiv serial flash clock speed selection cctl 2 sft serial flash type cctl 2 mt memory type (dram, flash) cctl 1 cs9 small dram (<2m) cctl 1 sas 2mx8 (or 1mx16) aram/dram md 0 /sclk md 2 /sdo md 1 /sdi md 4 /cs 0 sk do tc 58 a 040 f di cs sk do di cs sk do di cs md 5 /cs 1 md 6 /cs 2 psb 4860
psb 4860 data sheet 137 2000-01-14 2.4.6 auxiliary parallel port the provides an auxiliary parallel port if the memory interface is in serial flash or samsung flash mode. in this case the lines ma 0 to ma 15 (one flash device) or ma 0 to ma 7 and ma 12 to ma 15 are not needed for the memory interface and can therefore be used for an auxiliary parallel port. the auxiliary parallel port has two modes: static mode and multiplex mode. in both modes, the can generate an interrupt on specific input pins and specific signal edges. each input pin can be masked individually. the events that generated an interrupt are collected in a hold register. table 103 shows the registers for mode selection. 2.4.6.1 static mode in static mode all pins of the auxiliary parallel port interface have identical functionality. any pin can be configured as an output or an input. pins configured as outputs provide a static signal as programmed by the controller. pins configured as inputs are monitoring the signal continuously without latching. the controller always reads the current value. table 104 shows the registers used for static mode. 2.4.6.2 multiplex mode in multiplex mode, the multiplexes either four output registers or three output register and one input to ma 0 -ma 11. for this, ma 12 -ma 15 are used to distinguish four timeslots. each timeslot has a duration of approximately 2 ms. the timeslots are separated by a gap of approximately 125 s, in which none of the signals ma 12 -ma 15 are active. the multiplexes three output registers to ma 0 -ma 11 in timeslots 0, 1 and 2. in timeslot 3, the direction of the pins can be programmed. for input pins, the signal is latched with the falling edge of ma 12 . table 105 shows the registers used for multiplex mode. this mode is useful for scanning keys or controlling seven segment led displays. table 103 auxiliary parallel port mode registers register name comment hwconfig1 app mode selection (static/multiplex) hwconfig3 mpm enable four flash select lines instead of ma 8 -ma 11 table 104 static mode registers register # of bits comment dout3 16 output signals (for pins configured as outputs) din 16 input signals (for pins configured as inputs) ddir 16 pin direction
psb 4860 data sheet 138 2000-01-14 figure 80 shows the timing diagram for multiplex mode. figure 80 auxiliary parallel port - multiplex mode note: in either mode the voltage at any pin (ma 0 to ma 15 ) must not exceed v dd. 2.4.6.3 interrupt generation for each pin configured as an input, the compares the current value to the previous value. in static mode, the previous value is the value 1 ms ago (static mode). in multiplex mode, the previous value is the value sampled during the previous input timeslot. in both modes, the exact sampling point cannot be defined. for a reliable detection of a specific value, it is therefore necessary that a value must be stable at least 1.5 ms (static mode) or 8 ms (multiplex mode). table 105 multiplex mode registers register # of bits comment dout0 12 output signals on ma 0 -ma 11 while ma 15 =1 dout1 12 output signals on ma 0 -ma 11 while ma 14 =1 dout2 12 output signals on ma 0 -ma 11 while ma 13 =1 dout3 12 output signals (for pins configured as outputs) while ma 12 =1 din 12 input signals (for pins configured as inputs) at falling edge of ma 12 ddir 12 pin direction during ma 12 =1 2 ms ma 15 ma 14 ma 13 ma 12 ma 0 -ma 11 dout0 dout2 dout1 dout0 din/dout3
psb 4860 data sheet 139 2000-01-14 for each input pin the can be programmed to detect the following changes individually (table 106 ). whenever an input pin meets the specified condition then the sets the corresponding bit within the register dhold and also the ipp bit of the status register. therefore the register dhold collects all input pins that have met the programmed condition while the status register collects all events at any pin. the change of bit status:ppi can also trigger an external interrupt depending on the mask register intm. the bit status:ipp is reset when the register dhold is read by the controller. the register dhold is also cleared at this time (i.e. when it is read). note: the edge detection can be stopped by writing 0 to the register dhold. writing any other value to dhold starts the edge detection according to the programmed masks. edge detection must be started after a wake-up as it is disabled by default. table 106 interrupt mask definition for parallel port dmask1 dmask2 prev. value cur. value remark 0 0 - - disabled 0 1 0 1 rising edge 1 0 1 0 falling edge 1 1 0 (1) 1 (0) both edges
psb 4860 data sheet 140 2000-01-14
psb 4860 data sheet 141 2000-01-14 3 detailed register description the has a single status register (read only) and an array of data registers (read/write). the purpose of the status register is to inform the external microcontroller of important status changes of the and to provide a handshake mechanism for data register reading or writing. if the generates an interrupt, the status register contains the reason of the interrupt. 3.1 status register rdy ready 0: the last command (if any) is still in progress. 1: the last command has been executed. abt abort 0: no exception during operation 1: an exception caused the to abort any operation currently in progress. the abt bit is cleared by writing the revision register. no other command is accepted by the while abt is set. gap gap being detected 0: currently no gap is being detected during recording 1: currently a gap is being detected during recording vox vox detection 0: the input signal of the speech coder contains voice 1: the input signal represents silence, noise, constant or periodic signals cia caller id available 0: no new data for caller id 1: new caller id byte available cir caller id request 0: no new data for caller id sender requested 1: new caller id byte requested 15 0 rdy abt gap vox cia cir cd cis cpt utd cng sd err bsy dtv atv da drq pqe ppi
psb 4860 data sheet 142 2000-01-14 cd carrier detect 0: no carrier detected 1: carrier detected cis caller id stop bits 0: the caller id sender st ill sends data 1: the caller id sender sends stop bits cpt call progress tone 0: currently no call progress tone detected or pause detected (raw mode) 1: currently a call progress is detected utd universal tone detected 0: currently no tone is being detetced 1: currently a tone is being detected cng fax calling tone 0: currently no fax calling tone is being detected 1: currently a fax calling tone is being detected sd speech detected 0: no speech detected 1: speech signal at input of coder err error (file command) 0: no error 1: last file command has resulted in an error bsy busy (file command) 0: file system idle 1: file system still busy (also set during encoding/decoding) dtv dtmf tone valid 0: no new dtmf code available 1: new dtmf code available in ddctl atv alert tone valid 0: no new alert tone code available
psb 4860 data sheet 143 2000-01-14 1: new alert tone code available in adctl0 da data available 0: no data available 1: data of speech encoder to be fetched by microcontroller drq data request 0: no data requested 1: new data for speech decoder requested from the microcontroller pqe phrase queue empty 0: no new phrase requested 1: new phrase number requested for continuous phrase playing ppi parallel port interrupt 0: no unmasked change at input ports of parallel port 1: at least one unmasked input has changed at the parallel port
psb 4860 data sheet 144 2000-01-14 3.2 hardware configuration registers hwconfig 0 - hardware configuration register 0 ppsdx push/pull for sdx 0: the sdx pin has open-drain characteristic 1: the sdx pin has push/pull characteristic ppint push/pull for int 0: the int pin has open-drain characteristic 1: the int pin has push/pull characteristic pfrdy pullup for frdy 0: the internal pullup resistor of pin frdy is enabled 1: the internal pullup resistor of frdy is disabled ppsdi push/pull for sdi interface 0: the du and dd pins have open-drain characteristic 1: the du and dd pins have push/pull characteristic osc enable auxiliary oscillator 0: the auxiliary oscillator (osc 1 , osc 2 ) is disabled 1: the auxiliary oscillator (osc 1 , osc 2 ) is enabled rtc enable real time clock 0: the real time clock is disabled 1: the real time clock (rtc) is enabled. acs afe clock source 0: afeclk is derived from the main oscillator 1: afeclk is derived from the clk input pd power down (read only) 0: the is in active mode 1: the is in power down mode 7 0 pd acs rtc osc ppsdi pfrdy ppint ppsdx
psb 4860 data sheet 145 2000-01-14 hwconfig 1 - hardware configuration register 1 app auxiliary parallel port act afe clock tracking 0: afeclk tracking disabled 1: afeclk tracking enabled ads afe double speed 0: 8 khz afefs 1: 16 khz afefs mfs master frame sync selection 0: afefs 1: fsc xtal xtal frequency ssdi ssdi interface selection 0: iom ? -2 interface 1: ssdi interface 7 0 app act ads mfs xtal ssdi 76description 0 0 normal (aram/dram, intel type flash, voice prompt eprom) 0 1 app static mode 1 0 app multiplex mode 1 1 reserved 21factor p 1) 1) the factor p is needed to calculate the clock frequency at afeclk. description 0 0 5 34.560 mhz 0 1 4.5 31.104 mhz 104 reserved 1 1 reserved reserved
psb 4860 data sheet 146 2000-01-14 hwconfig 2 - hardware configuration register 2 ppm push/pull for memory interface (reset, power down) 0: the signals for the memory interface have push/pull characteristic 1: the signals for the memory interface have pullup/pulldown characteristic esdx edge select for dx 0: du/dx is transmitted with the rising edge of dcl 1: du/dx is transmitted with the falling edge of dcl esdr edge select for dr 0: dd/dr is latched with the falling edge of dcl 1: dd/dr is latched with the rising edge of dcl rsel refresh select 7 0 ppm esdx esdr 0 0 0 rsel 10description 0 0 64 khz refresh frequency 0 1 32 khz refresh frequency 1 0 16 khz refresh frequency 1 1 8 khz refresh frequency
psb 4860 data sheet 147 2000-01-14 hwconfig 3 - hardware configuration register 3 lcm low clock mode 0: normal xtal frequency range 1: 15.368 mhz xtal frequency sfi serial flash interface 0: md 0 -md 7 are used for aram/dram or parallel flash interface 1: md 0 -md 7 are used for serial flash interface mpm mixed port mode 0: app interface compatible with psb 4860 v2.1 1: ma 0 -ma 7 and ma 12 -ma 15 are app, ma 8 -ma 11 select flash devices 7 0 0 0 0 lcm sfi mpm 0 0
psb 4860 data sheet 148 2000-01-14 3.3 read/write registers the following sections contains all read/write registers of the . the register addresses are given as hexadecimal values. registers marked with an r are affected by reset or a wake up after power down. all other registers retain their previous value. no access must be made to addresses other than those associated with a read/write register. 3.3.1 register table address. name long name page 00h rev revision ............................................................................. 153 01h r cctl chip control ...................................................................... 154 02h r intm interrupt mask register ..................................................... 156 03h r afectl analog front end interface control ................................... 157 04h r ifs1 interface select 1 .............................................................. 158 05h r ifg1 interface gain 1 ................................................................. 159 06h r ifg2 interface gain 2 ................................................................. 160 07h r ifs2 interface select 2 .............................................................. 161 08h r ifg3 interface gain 3 ................................................................. 162 09h r ifg4 interface gain 4 ................................................................. 163 0ah r sdconf serial data interface configuration ................................... 164 0bh r sdchn1 serial data interface channel 1 ........................................ 165 0chr ifs3 interface select 3 .............................................................. 167 0dhr sdchn2 serial data interface channel 2 ........................................ 168 0eh r ifs4 interface select 4 .............................................................. 169 0fh r ifg5 interface gain 5 ................................................................. 170 10h r ua universal attenuator .......................................................... 171 11h r dgctl dtmf generator control ................................................... 172 12h dgf1 dtmf generator frequency 1 .......................................... 173 13h dgf2 dtmf generator frequency 2 .......................................... 174 14h dgl dtmf generator level ...................................................... 175 15h dgatt dtmf generator attenuation ............................................ 176 16h r cngctl calling tone control .......................................................... 177 17h cngbt cng burst time ................................................................ 178 18h cnglev cng minimal signal level ................................................ 179 19h cngres cng signal resolution ..................................................... 180 1ah r atdctl0 alert tone detection 0 ....................................................... 181 1bh atdctl1 alert tone detection 1 ....................................................... 182 1chr cidctl0 caller id control 0 ............................................................. 183 1dh cidctl1 caller id control 1 ............................................................. 184 1eh r ifs5 interface select 5 .............................................................. 185 1fh r ifg6 interface gain 6 ................................................................. 186 20h r cptctl call progress tone control ............................................... 187 21h cpttr call progress tone thresholds ......................................... 188
psb 4860 data sheet 149 2000-01-14 22h cptmn cpt minimum times ..........................................................189 23h cptmx cpt maximum times .........................................................190 24h cptdt cpt delta times ................................................................191 25h r lecctl line echo cancellation control ..........................................192 26h leclev minimal signal level for line echo cancellation ...............193 27h lecatt externally provided attenuation .........................................194 28h lecmgn margin for double talk detection .......................................195 29h r ddctl dtmf detector control ......................................................196 2ah ddtw dtmf detector signal twist ..............................................197 2bh ddlev dtmf detector minimum signal level ..............................198 2eh r fcfctl equalizer control ................................................................199 2fh fcfcof equalizer coefficient data ..................................................201 30h r scctl speech coder control ........................................................202 31h scct2 speech coder control 2 .....................................................203 32h scct3 speech coder control 3 .....................................................204 33h scdata speech encoder data ........................................................205 34h r sdctl speech decoder control ....................................................206 35h sdct2 speech decoder control 2 .................................................207 36h sddata speech decoder data ........................................................208 38h r agcctl agc control .......................................................................209 39h agcatt automatic gain control attenuation ...................................210 3ah agc1 automatic gain control 1 ...................................................211 3bh agc2 automatic gain control 2 ...................................................212 3ch agc3 automatic gain control 3 ...................................................213 3dh agc4 automatic gain control 4 ...................................................214 3eh agc5 automatic gain control 5 ...................................................215 40h r fctl file control .........................................................................216 41h r fcmd file command ....................................................................217 42h r fdata file data .............................................................................219 43h r fptr file pointer .........................................................................220 45h r pdctl peak detector control ........................................................221 46h pddata peak detector data ............................................................222 47h r spsctl sps control .......................................................................223 48h r rtc1 real time clock 1 ..............................................................224 49h r rtc2 real time clock 2 ..............................................................225 4ah r dout0 data out (timeslot 0) .........................................................226 4bh r dout1 data out (timeslot 1) .........................................................227 4chr dout2 data out (timeslot 2) .........................................................228 4dhr dout3 data out (timeslot 3 or static mode) .................................229 4eh din data in (timeslot 3 or static mode) ...................................230 4fh r ddir data direction (timeslot 3 or static mode) ........................231 50h dmask1 data in mask 1 (timeslot 3 or static mode) .......................232 51h dmask2 data in mask 2 (timeslot 3 or static mode) .......................233
psb 4860 data sheet 150 2000-01-14 52h r dhold data in hold (timeslot 3 or static mode) .......................... 234 53h scvox1 vox detector 1 ................................................................... 235 54h scvox2 vox detector 2 ................................................................... 236 55h scvox3 vox detector 3 ................................................................... 237 56h scvox4 vox detector 4 ................................................................... 238 57h scvox5 vox detector 5 ................................................................... 239 58h scvox6 vox detector 6 ................................................................... 240 5ah scgap1 speech coder gap control 1 ............................................ 241 5bh scgap2 speech coder gap control 2 ............................................ 242 5ch scgap3 speech coder gap control 3 ............................................ 243 5dh scgap4 speech coder gap control 4 ............................................ 244 60h r sctl speakerphone control ...................................................... 245 62h r ssrc1 speakerphone source 1 .................................................... 246 63h r ssrc2 speakerphone source 2 .................................................... 247 64h ssdx1 speech detector (transmit) 1 ........................................... 248 65h ssdx2 speech detector (transmit) 2 ........................................... 249 66h ssdx3 speech detector (transmit) 3 ........................................... 250 67h ssdx4 speech detector (transmit) 4 ........................................... 251 68h ssdr1 speech detector (receive) 1 ............................................ 252 69h ssdr2 speech detector (receive) 2 ............................................ 253 6ah ssdr3 speech detector (receive) 3 ............................................ 254 6bh ssdr4 speech detector (receive) 4 ............................................ 255 6ch sscas1 speech comparator (acoustic side) 1 .............................. 256 6dh sscas2 speech comparator (acoustic side) 2 .............................. 257 6eh sscas3 speech comparator (acoustic side) 3 .............................. 258 6fh sscls1 speech comparator (line side) 1 ..................................... 259 70h sscls2 speech comparator (line side) 2 ..................................... 260 71h sscls3 speech comparator (line side) 3 ..................................... 261 72h satt1 attenuation unit 1 .............................................................. 262 73h satt2 attenuation unit 2 .............................................................. 263 74h sagx1 automatic gain control (transmit) 1 ................................. 264 75h sagx2 automatic gain control (transmit) 2 ................................. 265 76h sagx3 automatic gain control (transmit) 3 ................................. 266 77h sagx4 automatic gain control (transmit) 4 ................................. 267 78h sagx5 automatic gain control (transmit) 5 ................................. 268 79h sagr1 automatic gain control (receive) 1 .................................. 269 7ah sagr2 automatic gain control (receive) 2 .................................. 270 7bh sagr3 automatic gain control (receive) 3 .................................. 271 7ch sagr4 automatic gain control (receive) 4 .................................. 272 7dh sagr5 automatic gain control (receive) 5 .................................. 273 7eh slga line gain ........................................................................... 274 80h saelen acoustic echo cancellation length ................................... 275 81h saeatt acoustic echo cancellation double talk attenuation ....... 276
psb 4860 data sheet 151 2000-01-14 82h saegs acoustic echo cancellation global scale ..........................277 83h saeps1 acoustic echo cancellation partial scale ..........................278 84h saeps2 acoustic echo cancellation first block ..............................279 9ah r cidmf1 caller id message format .................................................280 9bh r cidmf2 caller id message format .................................................281 9chr cidmf3 caller id message format .................................................282 9dhr cidmf4 caller id message format .................................................283 9eh r cidmf5 caller id message format .................................................284 9fh r cidmf6 caller id message format .................................................285 a0h r utdctl universal tone detector control ........................................286 a1h utdcf center frequency for utd .................................................287 a2h utdbw band width for utd ...........................................................288 a3h utdlim limiter limit for utd ..........................................................289 a4h utdlev minimal signal level for utd .............................................290 a5h utddlt minimum difference for utd ..............................................291 a6h utdtmt tone times for utd ...........................................................292 a7h utdtmg gap times for utd ............................................................293 aahr cisctl caller id sender control ....................................................294 abh cisdata data byte for caller id sender ...........................................295 ach cislev level of signal for caller id sender ...................................296 adh cisszr number of seizure bits ......................................................297 aeh cismrk number of mark bits ..........................................................298 note: registers cctl, rtc1, rtc2, dout0, dout1, dout2, dout3 and ddir are only affected by reset, not by wakeup. for register spsctl see the register description for the exact behaviour. 3.3.2 register naming conventions several registers contain one or more fields for input signal selection. all fields labelled i 1 (i 2 , i 3 ) are five bits wide and use the same coding as shown in table 107 . values not shown in the table are reserved. table 107 signal encoding 43210signaldescription 00000s 0 silence 00001s 1 analog line input (channel 1 of psb 4851 interface) 00010s 2 analog line output (channel 1 of psb 4851 interface) 00011s 3 microphone input (channel 2 of psb 4851 interface) 00100s 4 loudspeaker/handset output (channel 2 of psb 4851 interface)
psb 4860 data sheet 152 2000-01-14 00101s 5 serial interface input, channel 1 00110s 6 serial interface output, channel 1 00111s 7 serial interface input, channel 2 01000s 8 serial interface output, channel 2 01001s 9 dtmf generator output 01010s 10 dtmf generator auxiliary output 01011s 11 speakerphone output (acoustic side) 01100s 12 speakerphone output (line side) 01101s 13 speech decoder output 01110s 14 universal attenuator output 01111s 15 line echo canceller output 10000s 16 agc unit output (after agc) 10001s 17 agc unit output (before agc) 10010s 18 equalizer output 10110s 22 caller id sender output 10111s 23 serial interface input, channel 3 11000s 24 serial interface output, channel 3 table 107 signal encoding 43210signaldescription
psb 4860 data sheet 153 2000-01-14 00 h rev revision the revision register can only be read. note: a write access to the revision register does not change its content. it does, however, clear the abt bit of the status register. 15 0 0001001100000000
psb 4860 data sheet 154 2000-01-14 01 h r cctl chip control cdiv clock division for serial flash interface (md 0 /sclk frequency) sft serial flash type mv voice prompt directory 0: not available 1: available (within eprom or flash) em emergency mode 0: normal mode 1: enter emergency mode pd power down 0: is in active mode 1: enter power-down mode 15 0 cdiv sft mv em 0 pd 0 0 0 mq mt cs9 sas reset value 0000000000000000 15 14 description example (xtal=31.104 mhz) 0 0 xtal:8 3.9 mhz 0 1 xtal:16 1.9 mhz 1 0 xtal:32 1 mhz 1 1 xtal:64 500 khz 13 12 description 0 0 none 01toshiba 10atmel
psb 4860 data sheet 155 2000-01-14 mq memory quality 0: aram 1: dram mt memory type cs9 cas selection 0: other memory 1: 256kx4 or 512kx8 memory sas split address space 0: other aram/dram 1: two 2mx8 devices 32description 0 0 aram/dram 0 1 serial flash memory 1 1 samsung flash memory
psb 4860 data sheet 156 2000-01-14 02 h r intm interrupt mask register if a bit of this register is set to 0, the corresponding bit of the status register does not generate an interrupt. if a bit of this register is set to 1, an external interrupt can be generated by the corresponding bit of the status register. 15 0 rdy 1 gap vox cia cir cd cis cpt utd cng sd 0 bsy dtv atv da drq pqe ppi reset value 0100000000000000
psb 4860 data sheet 157 2000-01-14 03 h r afectl analog front end interface control als loudspeaker amplification this value is transferred on channel c3 of the afe interface. if the psb 4851 is used it represents the amplification of the loudspeaker amplifier. en interface enable 0: afe interface disabled 1: afe interface enabled 15 0 0000 als 0000000en reset value 0000 0 00000000
psb 4860 data sheet 158 2000-01-14 04 h r ifs1 interface select 1 the signal selection fields i1, i2 and i3 of ifs1 determine the outgoing signal of channel 1 of the analog interface. for the psb 4851 this is usually the line out signal. the hp bit enables a high-pass for the incoming signal of channel 1 of the analog interface. for the psb 4851 this is usually the line in signal. hp high-pass for s 1 0: disabled 1: enabled i1 input signal 1 for ig2 i2 input signal 2 for ig2 i3 input signal 3 for ig2 note: as all sources are always active, unused sources must be set to 0 (s 0 ). 15 0 hp i1 i2 i3 reset value 00 0 0
psb 4860 data sheet 159 2000-01-14 05 h r ifg1 interface gain 1 ifg1 is associated with the incoming signal of channel 1 of the analog interface. for the psb 4851 this is usually the line in signal. ig1 in order to obtain a gain g the parameter ig1 can be calculated by the following formula: 15 0 0ig1 reset value 0 8192 (0 db) ig1 32768 g 12.04 db ? () 20 db ? 10 =
psb 4860 data sheet 160 2000-01-14 06 h r ifg2 interface gain 2 ifg2 is associated with the outgoing signal of channel 1 of the analog interface. for the psb 4851 this is usually the line out signal. ig2 gain of amplifier ig2 in order to obtain a gain g the parameter ig2 can be calculated by the following formula: 15 0 0ig2 reset value 0 8192 (0 db) ig2 32768 g 12.04 db ? () 20 db ? 10 =
psb 4860 data sheet 161 2000-01-14 07 h r ifs2 interface select 2 the signal selection fields i1, i2 and i3 of ifs2 determine the outgoing signal of channel 2 of the analog interface. for the psb 4851 this is usually the loudspeaker signal. the hp bit enables a high-pass for the incoming signal of channel 2 of the analog interface. for the psb 4851 this is usually the microphone signal. hp high-pass for s 3 0: disabled 1: enabled i1 input signal 1 for ig4 i2 input signal 2 for ig4 i3 input signal 3 for ig4 note: as all sources are always active, unused sources must be set to 0 (s 0 ). 15 0 hp i1 i2 i3 reset value 0000
psb 4860 data sheet 162 2000-01-14 08 h r ifg3 interface gain 3 ifg3 is associated with the incoming signal of channel 2 of the analog interface. for the psb 4851 this is usually the microphone signal. ig3 gain of amplifier ig3 in order to obtain a gain g the parameter ig3 can be calculated by the following formula: 15 0 0ig3 reset value 0 8192 (0 db) ig3 32768 g 12.04 db ? () 20 db ? 10 =
psb 4860 data sheet 163 2000-01-14 09 h r ifg4 interface gain 4 ifg4 is associated with the outgoing signal of channel 2 of the analog interface. for the psb 4851 this is usually the loudspeaker signal. ig4 gain of amplifier ig4 in order to obtain a gain g the parameter ig4 can be calculated by the following formula: 15 0 0ig4 reset value 0 8192 (0 db) ig4 32768 g 12.04 db ? () 20 db ? 10 =
psb 4860 data sheet 164 2000-01-14 0a h r sdconf serial data interface configuration nts number of timeslots dcl double clock mode 0: single clock mode 1: double clock mode en enable interface 0: interface is disabled (both channels) 1: interface is enabled (depending on separate channel enable bits) 15 0 00 nts 00000dcl0en reset value 00 0 00000000 13 12 11 10 9 8 description 0000001 0000012 ... ... ... ... ... ... ... 11111164
psb 4860 data sheet 165 2000-01-14 0b h r sdchn1 serial data interface channel 1 nas number of active drst strobe (ssdi interface mode) pcd pcm code 0: a-law 1: -law en enable interface 0: interface is disabled 1: interface is enabled if sdconf:en=1 pcm pcm mode 0: 16 bit linear coding (two timeslots) 1: 8 bit pcm coding (one timeslot) dd data direction 0: dd: data downstream, du: data upstream 1: dd: data upstream, du: data downstream ts timeslot for channel 1 15 0 nas 0 0 pcd en pcm dd ts reset value 0 0 00000 0 15 14 13 12 description 00001 ... ... ... ... ... 111116 543210description 0000000
psb 4860 data sheet 166 2000-01-14 note: if pcm=0 then ts denotes the first timeslot of the two consecutive timeslots used. only even timeslots are allowed in this case. ... ... ... ... ... ... ... 11111163 543210description
psb 4860 data sheet 167 2000-01-14 0c h r ifs3 interface select 3 the signal selection fields i1, i2 and i3 of ifs3 determine the outgoing signal of channel 1 of the iom/ssdi-interface. the hp bit enables a high-pass for the incoming signal of channel 1 of the analog iom ? - 2/ssdi-interface. hp high-pass for s 5 0: disabled 1: enabled i1 input signal 1 for s 6 i2 input signal 2 for s 6 i3 input signal 3 for s 6 note: as all sources are always active, unused sources must be set to 0 (s 0 ). 15 0 hp i1 i2 i3 reset value 0000
psb 4860 data sheet 168 2000-01-14 0d h r sdchn2 serial data interface channel 2 cs channel split 0: single 16 bit or single 8 bit channel 1: two adjacent 8 bit channels (sdchn2:pcm must be set to 0) pcd pcm code (for both 8 bit channels if cs=1) 0: a-law 1: -law en enable interface 0: interface is disabled 1: interface is enabled if sdconf:en=1 pcm pcm mode 0: 16 bit linear coding (two timeslots) 1: 8 bit pcm coding (one timeslot) dd data direction 0: dd: data downstream, du: data upstream 1: dd: data upstream, du: data downstream ts timeslot for channel 2 note: if pcm=0 then ts denotes the first timeslot of the two consecutive timeslots used. only even timeslots are allowed in this case. 15 0 cs00000pcdenpcmdd ts reset value 0000000000 0 543210description 0000000 0000011 ... ... ... ... ... ... ... 11111163
psb 4860 data sheet 169 2000-01-14 0e h r ifs4 interface select 4 the signal selection fields i1, i2 and i3 of ifs4 determine the outgoing signal of channel 2 of the iom ? -2/ssdi-interface. the hp bit enables a high-pass for the incoming signal of channel 2. hp high-pass for s 7 0: disabled 1: enabled i1 input signal 1 for s 8 i2 input signal 2 for s 8 i3 input signal 3 for s 8 note: as all sources are always active, unused sources must be set to 0 (s 0 ). 15 0 hp i1 i2 i3 reset value 0000
psb 4860 data sheet 170 2000-01-14 0f h r ifg5 interface gain 5 att1 attenuation for i3 (channel 1) in order to obtain an attenuation a [db] at i3 of channel 1 of the iom ? -2/ssdi interface (s 6 ), the parameter att1 can be calculated by the following formula: att2 attenuation for i3 (channel 2) in order to obtain an attenuation a [db] at i3 of channel 2 of the iom ? -2/ssdi interface (s 6 ), the parameter att1 can be calculated by the following formula: 15 0 att1 att2 reset value 255 (0 db) 255 (0 db) att1 256 a20db ? 10 = att2 256 a20db ? 10 =
psb 4860 data sheet 171 2000-01-14 10 h r ua universal attenuator att attenuation for ua for a given attenuation a [db] the parameter att can be calculated by the following formula: i1 input selection for ua 15 0 att 0 0 0 i1 reset value 0 (-100 db) 0 0 0 0 att 256 a20db ? 10 =
psb 4860 data sheet 172 2000-01-14 11 h r dgctl dtmf generator control en generator enable 0: disabled 1: enabled md mode 0: raw 1: cooked dtc dial tone code (cooked mode) 15 0 enmd0000000000 dtc reset value 000000000000 0 3 2 1 0 digit frequency 0 0 0 0 1 697/1209 0 0 0 1 2 697/1336 0 0 1 0 3 697/1477 0 0 1 1 a 697/1633 0 1 0 0 4 770/1209 0 1 0 1 5 770/1336 0 1 1 0 6 770/1477 0 1 1 1 b 770/1633 1 0 0 0 7 852/1209 1 0 0 1 8 852/1336 1 0 1 0 9 852/1477 1 0 1 1 c 852/1633 1 1 0 0 * 941/1209 1 1 0 1 0 941/1336 1 1 1 0 # 941/1477 1 1 1 1 d 941/1633
psb 4860 data sheet 173 2000-01-14 12 h dgf1 dtmf generator frequency 1 frq frequency of generator 1 the parameter frq for a given frequency f [hz] can be calculated by the following formula: 15 0 0frq frq 32768 f 4000hz ------------------- =
psb 4860 data sheet 174 2000-01-14 13 h dgf2 dtmf generator frequency 2 frq frequency of generator 2 the parameter frq for a given frequency f [hz] can be calculated by the following formula: 15 0 0frq frq 32768 f 4000hz ------------------- =
psb 4860 data sheet 175 2000-01-14 14 h dgl dtmf generator level lev2 signal level of generator 2 in order to obtain a signal level l (relative to the pcm maximum value) for generator 2 the value of lev2 can be calculated according to the following formula: lev1 signal level of generator 1 in order to obtain a signal level l (relative to the pcm maximum value) for generator 1 the value of lev1 can be calculated according to the following formula: 15 0 0lev20lev1 lev2 128 l20db ? 10 = lev1 128 l20db ? 10 =
psb 4860 data sheet 176 2000-01-14 15 h dgatt dtmf generator attenuation att2 attenuation of signal s 10 in order to obtain attenuation a the parameter att2 can be calculated by the formula: att1 attenuation of signal s 9 in order to obtain attenuation a the parameter att1 can be calculated by the formula: 15 0 att2 att1 att2 128 1024 a20db ? 10 +a18 ? 1db , < ; 128 a20db ? 10 a 18 ? 1db , > ; = att1 128 1024 a20db ? 10 +a18 ? 1db , < ; 128 a20db ? 10 a 18 ? 1db , > ; =
psb 4860 data sheet 177 2000-01-14 16 h r cngctl calling tone control en enable 0: cng unit disabled 1: cng unit enabled i1 input selection for calling tone detector 15 0 en0000000000 i1 reset value 00000000000 0
psb 4860 data sheet 178 2000-01-14 17 h cngbt cng burst time time minimum time for calling tone in order to obtain the parameter time for a minimum time t [ms] the following formula can be used: 15 0 0time time t 0.125 ms ? =
psb 4860 data sheet 179 2000-01-14 18 h cnglev cng minimal signal level min minimum signal level for calling tone in order to obtain the parameter min for a minimum signal level l [db] the following formula can be used: 15 0 00 min min 16384 l20db ? 10 =
psb 4860 data sheet 180 2000-01-14 19 h cngres cng signal resolution res signal resolution the parameter res depends on the noise level l [db] as follows: 15 0 1111 res res 4096 ? l20db ? 10 =
psb 4860 data sheet 181 2000-01-14 1a h r atdctl0 alert tone detection 0 en enable alert tone detection 0: the alert tone detection is disabled 1: the alert tone detection is enabled i1 input signal selection atc alert tone code 15 0 en00 i1 000000 atc reset value 000 0 000000 - 1) 1) undefined 10 description 0 0 no tone 0 1 2130 1 0 2750 1 1 2130/2750
psb 4860 data sheet 182 2000-01-14 1b h atdctl1 alert tone detection 1 md alert tone detection mode 0: only dual tones will be detected 1: either dual or single tones will be detected dev maximum frequency deviation for alert tone 0: 0.5% 1: 1.1% onh on hook 0: off hook 1: on hook min minimum level of alert tone signal for a minimum signal level min [db] the parameter min is given by the following formula: 15 0 md00dev000onh min min 2560 min 20 db ? 10 =
psb 4860 data sheet 183 2000-01-14 1c h r cidctl0 caller id control 0 en cid enable 0: disabled 1: enabled dot drop out tolerance 0: drop out during mark or seizure sequence aborts recognition 1: drop out tolerance during mark or seizure sequence. cm compatibilitiy mode 0: standard caller id decoder 1: improved caller id decoder i1 input signal selection data last received data byte 15 0 en dot cm i1 data reset value 000 0 0
psb 4860 data sheet 184 2000-01-14 1d h cidctl1 caller id control 1 nmb minimum number of mark bits nmss minimum number of mark/space sequences min minimum signal level for cid decoder for a minimum signal level min [db] the parameter min is given by the following formula: 15 0 nmb nmss min 15 14 13 12 11 description 000000 0000110 0001020 ... ... ... ... ... ... 11111310 10 9 8 7 6 description 000001 0000111 0001021 ... ... ... ... ... 11111311 min 640 min 20 db ? 10 =
psb 4860 data sheet 185 2000-01-14 1e h r ifs5 interface select 5 the signal selection fields i1, i2 and i3 of ifs5 determine the outgoing signal of channel 3 of the iom/ssdi-interface. the hp bit enables a high-pass for the incoming signal of channel 3. hp high-pass for s 23 0: disabled 1: enabled i1 input signal 1 for s 24 i2 input signal 2 for s 24 i3 input signal 3 for s 24 note: as all sources are always active, unused sources must be set to 0 (s 0 ). 15 0 hp i1 i2 i3 reset value 0000
psb 4860 data sheet 186 2000-01-14 1f h r ifg6 interface gain 6 att3 attenuation for i3 (channel 3) in order to obtain an attenuation a [db] the parameter att3 can be calculated by the following formula: 15 0 att3 00000000 reset value 255 (0db) 00000000 att3 256 a20db ? 10 =
psb 4860 data sheet 187 2000-01-14 20 h r cptctl call progress tone control en cpt detector enable 0: disabled 1: enabled md cpt mode 0: raw 1: cooked i1 input signal selection 15 0 enmd000000000 i1 reset value 00000000000 0
psb 4860 data sheet 188 2000-01-14 21 h cpttr call progress tone thresholds num number of cycles sn minimal signal-to-noise ratio min minimum signal level for cpt detector 15 0 num 0 sn min 15 14 13 cooked mode raw mode 0 0 0 reserved 0 0 0 1 2 reserved ... ... ... ... reserved 1 1 1 8 reserved 11 10 9 8 description 11119db 100012db 010015db 001018db 000022db value description 64 h -30 db 60 h -32 db 7a h -34 db 74 h -36 db 70 h -38 db 89 h -40 db 85 h -42 db 80 h -44 db 9a h -46 db 95 h -48 db 90 h -50 db
psb 4860 data sheet 189 2000-01-14 22 h cptmn cpt minimum times minb minimum time for cpt burst the parameter minb for a minimal burst time tbmin [ms] can be calculated by the following formula: ming minimum time for cpt gap the parameter ming for a minimal burst time tgmin [ms] can be calculated by the following formula: 15 0 minb ming minb tbmin 32 ms ? 4 ------------------------------------- - = ming tgmin 32 ms ? 4 -------------------------------------- =
psb 4860 data sheet 190 2000-01-14 23 h cptmx cpt maximum times maxb maximum time for cpt burst the parameter maxb for a maximal burst time of tbmax [ms] can be calculated by the following formula: maxg maximum time for cpt gap the parameter maxg for a maximal burst time of tgmax [ms] can be calculated by the following formula: 15 0 maxb maxg maxb tbmax tbmin ? 8 ----------------------------------------- = maxg tgmax tgmin ? 8 ----------------------------------------- - =
psb 4860 data sheet 191 2000-01-14 24 h cptdt cpt delta times difb maximum time difference between consecutive bursts the parameter difb for a maximal difference of t [ms] of two burst durations can be calculated by the following formula: difg maximum time difference between consecutive gaps the parameter difg for a maximal difference of t [ms] of two gap durations can be calculated by the following formula: 15 0 difb difg difb t 2ms ---------- - = difg t 2ms ----------- =
psb 4860 data sheet 192 2000-01-14 25 h r lecctl line echo cancellation control en enable 0: disabled 1: enabled md mode 0: normal 1: extended cm compatibilitiy mode 0: standard line echo canceller 1: improved line echo canceller as adaption stop 0: adation enabled 1: adation stopped i1 input signal selection for i 1 i2 input signal selection for i 2 15 0 en md cm as 0 0 i1 i2 reset value 000000 0 0
psb 4860 data sheet 193 2000-01-14 26 h leclev minimal signal level for line echo cancellation min the parameter min for a minimal signal level l (db) can be calculated by the following formula: 15 0 0min min 512 96.3 l + () 5 log2 ---------------------------------------- =
psb 4860 data sheet 194 2000-01-14 27 h lecatt externally provided attenuation att the parameter att for an externally provided attenuation a (db) can be calculated by the following formula: note: att has a slightly different meaning in normal and in superior mode. in normal mode, it represents just the externally provided attenunation while in superior mode, it represents the externally provided attenuation minus a threshold. 15 0 0att att 512 a 5 log2 ------------------- =
psb 4860 data sheet 195 2000-01-14 28 h lecmgn margin for double talk detection mgn the parameter mgn for a margin of l (db) can be calculated by the following formula: note: mgm has a different meaning in normal and in superior mode. the formula above holds in any mode, though. 15 0 0mgn mgn 512 l 5 log2 ------------------- =
psb 4860 data sheet 196 2000-01-14 29 h r ddctl dtmf detector control en enable dtmf tone detection 0: the dtmf detection is disabled 1: the dtmf detection is enabled i1 input signal selection dtc dtmf tone code 15 0 en00 i1 000 dtc reset value 000 0 000 - 1) 1) undefined 43210 frequency digit 1 0 0 0 0 941 / 1633 d 1 0 0 0 1 697 / 1209 1 1 0 0 1 0 697 / 1336 2 1 0 0 1 1 697 / 1477 3 1 0 1 0 0 770 / 1209 4 1 0 1 0 1 770 / 1336 5 1 0 1 1 0 770 / 1477 6 1 0 1 1 1 852 / 1209 7 1 1 0 0 0 852 / 1336 8 1 1 0 0 1 852 / 1477 9 1 1 0 1 0 941 / 1336 0 1 1 0 1 1 941 / 1209 * 1 1 1 0 0 941 / 1477 # 1 1 1 0 1 697 / 1633 a 1 1 1 1 0 770 / 1633 b 1 1 1 1 1 852 / 1633 c
psb 4860 data sheet 197 2000-01-14 2a h ddtw dtmf detector signal twist twist signal twist for dtmf tone in order to obtain a minimal signal twist t the parameter twist can be calculated by the following formula: note: twist must be in the range [4096,20480], which corrsponds to [8.5 db,1.5 db]. 15 0 0twist twist 32768 0.5 db t + () ? () 10 db ? 10 =
psb 4860 data sheet 198 2000-01-14 2b h ddlev dtmf detector minimum signal level min minimum signal level note: values outside the given range are reserved and must not be used. 15 0 1111111111 min 543210 description 001110 -50db 001111 -49db ... ... ... ... ... ... ... 100001 -31db 100010 -30db
psb 4860 data sheet 199 2000-01-14 2e h r fcfctl equalizer control en enable equalizer 0: the equalizer is disabled 1: the equalizer is enabled adr coefficient address 15 0 en 0 adr 0 0 0 i reset value 00 0 000 0 13 12 11 10 9 8 coefficient 000000 a1 000001 a2 000010 a3 000011 a4 000100 a5 000101 a6 000110 a7 000111 a8 001000 a9 001001 b2 001010 b3 001011 b4 001100 b5 001101 b6 001 110 b7 001111 b8 010000 b9 010001 c1 010010 d1 010011 d2 010100 d3 010101 d4 01 0110 d5
psb 4860 data sheet 200 2000-01-14 i1 input signal selection 010111 d6 011000 d7 011001 d8 011010 d9 011011 d10 011100 d11 011101 d12 01 1 110 d13 011111 d14 100000 d15 100001 d16 100010 d17 100011 c2 13 12 11 10 9 8 coefficient
psb 4860 data sheet 201 2000-01-14 2f h fcfcof equalizer coefficient data v coefficient value for the coefficient a 1 -a 9 , b 2 -b 9 and d 1 -d 17 the following formula can be used to calculate v for a coefficient c : for the coefficients c 1 and c 2 the following formula can be used to calculate v for a coefficient c : 15 0 v v 32768 c =; -1c1 < v 128 c =; 1c256 <
psb 4860 data sheet 202 2000-01-14 30 h r scctl speech coder control en enable 0: disabled 1: enabled q1/q0 coder quality vc voice controlled start of recording 0: disabled 1: enabled vox vox enable 0: disabled 1: enabled gap gap coding 0: disabled 1: enabled i1 input signal selection (first input) i2 input signal selection (second input) 15 0 en q1 vc q0 vox gap i1 i2 reset value 000000 0 0 14 12 bit rate 0 0 3300 bit/s (average) 1 0 10300 bit/s (fixed) 1 1 5600 bit/s (fixed)
psb 4860 data sheet 203 2000-01-14 31 h scct2 speech coder control 2 time the parameter time for a time t ([ms]) can be calculated by the following formula: min the parameter min for a signal level l ([db]) can be calculated by the following formula: 15 0 time min time t 32 ----- - = min 16384 l 20 ----- - 10 =
psb 4860 data sheet 204 2000-01-14 32 h scct3 speech coder control 3 lp the parameter lp for a time constant of t ([ms]) can be calculated by the following formula: gapt the parameter gapt for a minimum gap time of t ([ms]) can be calculated by the following formula: 15 0 0 lp gapt lp 256 t -------- - = gapt t 2 -- - =
psb 4860 data sheet 205 2000-01-14 33 h scdata speech encoder data data if data transfer via sci is enabled with bit ssctl:sci, data is the data of the speach encoder that must be read by the microcontroller . 15 0 data
psb 4860 data sheet 206 2000-01-14 34 h r sdctl speech decoder control en enable 0: disabled 1: enabled cs change speed 0: all defined bits can be written 1: only the speed bit field is written (for on the fly changes) sci transfer speach data via sci 0: speach data is read from / written to aram/dram/flash 1: speach data is provided in register scdata/sddata for read/write by the microcontroller cp gap compression 0: gaps are played back at original length 1: gaps are skipped during replay cn gap comfort noise 0: disabled 1: enabled speed playback speed 15 0 en cs 1) 1) write only, reads as 0. 00000sci00cpcn00 speed reset value 00000000000000 0 1 0 description 0 0 normal speed 0 1 0.5 times normal speed 1 0 1.5 times normal speed 1 1 2.0 times normal speed
psb 4860 data sheet 207 2000-01-14 35 h sdct2 speech decoder control 2 cn the parameter cn for the noise level does not have a dimension. it is a linear scaling factor with 0 representing silence and 7fff h representing the maximum value. 15 0 0cn
psb 4860 data sheet 208 2000-01-14 36 h sddata speech decoder data data if data transfer via sci is enabled with bit ssctl:sci, data is the data for the speach decoder. the microcontroller must makle sure that this data is writtem there on request (bit status:drq). . 15 0 data
psb 4860 data sheet 209 2000-01-14 38 h r agcctl agc control en enable 0: disabled 1: enabled i1 input signal selection for i 1 i2 input signal selection for i 2 15 0 en00000 i1 i2 reset value 000000 0 0
psb 4860 data sheet 210 2000-01-14 39 h agcatt automatic gain control attenuation att the parameter att for an attenuation a ([db]) can be calculated by the following formula: 15 0 0att att 32768 a 20 ----- - 10 =
psb 4860 data sheet 211 2000-01-14 3a h agc1 automatic gain control 1 com the parameter com for a signal level l ([db]) can be calculated by the following formula: ag_init in order to obtain an initial gain g ([db]) the parameter ag_init can be calculated by the following formula: 15 0 com ag_init com 128 10 + l6622 , + 20 ------------------------ - l -42,14 db < ; 10 l4214 , + 20 ------------------------ - l -42,14 db > ; = ag_init 128 10 + g1806 , + 20 ------------------------- g 6 02 db , < ; 10 g602 , ? 20 --------------------- - g 6 02 db , > ; =
psb 4860 data sheet 212 2000-01-14 3b h agc2 automatic gain control 2 speedl the parameter speedl for a multiplication factor m is given by the following formula: speedh the parameter speedh for a multiplication factor m is given by the following formula: 15 0 speedl speedh speedl m 8192 = speedh m 256 =
psb 4860 data sheet 213 2000-01-14 3c h agc3 automatic gain control 3 ag_gain the parameter ag_gain for a gain g ([db]) can be calculated by the following formula: ag_att the parameter ag_att for an attenuation a ([db]) can be calculated by the following formula: 15 0 ag_gain 0 ag_att ag_gain 128 10 + g1806 , + 20 ------------------------- g602db , < ; 10 g602 , ? 20 --------------------- - g602db , > ; = ag_att 10 a4214 , + 20 ------------------------- =
psb 4860 data sheet 214 2000-01-14 3d h agc4 automatic gain control 4 dec the parameter dec for a time constant t ([1/ms]) is given by the following formula: lim the parameter lim for a signal level l ([db]) can be calculated by the following formula: 15 0 dec lim dec 256 t -------- - = lim 128 10 + l903 , + 20 --------------------- - l 66,22 db ? < ; 10 l6622 , + 20 ------------------------ - l 66,22 db ? > ; =
psb 4860 data sheet 215 2000-01-14 3e h agc5 automatic gain control 5 lp the parameter lp for a time constant t ([1/ms]) is given by the following formula: 15 0 000000001 lp lp 16 t ----- - =
psb 4860 data sheet 216 2000-01-14 40 h r fctl file control md mode 0: audio mode 1: binary mode ms memory space 0: r/w memory 1: voice prompt directory ts time stamp 0: no update of rtc1/rtc2 entry of file descriptor 1: rtc1/rtc2 entries are updated by content of rtc1/rtc2 registers. ud user data 0: user data word is not changed 1: the contents of fdata are written into the user data word. fno file number 15 0 0mdmstsud000 fno reset value 00000000 0
psb 4860 data sheet 217 2000-01-14 41 h r fcmd file command reb reserve emergency block 0: no 1: yes (initialize only) in initialize 0: no 1: yes (if cmd = 01111 or 11001) rd remap directory 0: no 1: yes ica immediate command abort 0: no 1: yes (file command currently in progress will be finished as fast as possible.) abt abort command 0: no 1: abort recompress or garbage collection cmd file command 15 0 rebinrdica0000abt00 cmd reset value 00000000000 0 43210description 00000open file 00001activate 00010seek 00011cut file 00100read data 00101write data
psb 4860 data sheet 218 2000-01-14 00110memory status 00111recompress file 0 1 0 0 0 read file descriptor - user 0 1 0 0 1 write file descriptor - user / rtc2 0 1 0 1 0 read file descriptor - rtc1 0 1 0 1 1 read file descriptor - rtc2 0 1 1 0 0 read file descriptor - len 0 1 1 0 1 garbage collection 01110open next free file 01111initialize 10000dma read 10001dma write 10010erase block 10011set address 1 0 1 0 0 delete multiple files 1 0 1 0 1 check voice prompt data integrity 1 1 0 0 0 write file descriptor - rtc1 / rtc 2 1 1 0 0 1 initialize message memory 43210description
psb 4860 data sheet 219 2000-01-14 42 h r fdata file data the fdata register contains the following information after a memory status command: free free blocks number of blocks (1 kbyte) currently usable for recording. np next phrase next phrase enable for phrase queuing. 15 0 free np 0 0 0 0 phrase selector reset value 0
psb 4860 data sheet 220 2000-01-14 43 h r fptr file pointer 15 0 file pointer 00000 phrase selector reset value 0
psb 4860 data sheet 221 2000-01-14 45 h r pdctl peak detector control en peak detector enable 0: disabled 1: enabled mm min/max 0: maximum 1: minimum i1 input signal selection 15 0 enmm000000000 i1 reset value 00000000000 0
psb 4860 data sheet 222 2000-01-14 46 h pddata peak detector data data maximum or minimum value of signal since last read access. note: this register can only be read. 15 0 data
psb 4860 data sheet 223 2000-01-14 47h r spsctl sps control pos position of status register window mode mode of sps interface sp1 direct control for sps 1 0: sps 1 set to 0 1: sps 1 set to 1 sp0 direct control for sps 0 0: sps 0 set to 0 1: sps 0 set to 1 note: if mode 1 has been selected prior to power-down, both mode 1 and the values of sp1 and sp0 are retained during power-down and wake-up. other modes are reset to 0 during power down. 15 0 pos 0000000 mode sp1sp0 reset value 0 0000000 0 - 1) 1) undefined - 1) 15 14 13 12 sps 0 sps 1 0000bit 0 bit 1 0001bit 1 bit 2 ... ... ... ... ... ... 1 1 1 0 bit 14 undefined 4 3 2 description 0 0 0 disabled (sps 0 and sps 1 zero) 0 0 1 output of sp1 and sp0 1 0 0 output of speakerphone state 1 0 1 expanded address output 1 1 0 output of status register
psb 4860 data sheet 224 2000-01-14 48 h r rtc1 real time clock 1 min minutes number of minutes elapsed in the current hour (0-59). sec seconds number of seconds elapsed in the current minute (0-59). 15 0 0000 min sec reset value 0000 0 0
psb 4860 data sheet 225 2000-01-14 49 h r rtc2 real time clock 2 day days number of days elapsed since last reset (0-2047). hr hours number of hours elapsed in the current day (0-23). 15 0 day hr reset value 00
psb 4860 data sheet 226 2000-01-14 4a h r dout0 data out (timeslot 0) data output data output data for pins ma 0 -ma 11 while ma 12 =1 (only if hwconfig1:app=10). 15 0 0000 data reset value 0000 0
psb 4860 data sheet 227 2000-01-14 4b h r dout1 data out (timeslot 1) data output data output data for pins ma 0 -ma 11 while ma 13 =1 (only if hwconfig1:app=10). 15 0 0000 data reset value 0000 0
psb 4860 data sheet 228 2000-01-14 4c h r dout2 data out (timeslot 2) data output data output data for pins ma 0 -ma 11 while ma 14 =1 (only if hwconfig1:app=10). 15 0 0000 data reset value 0000 0
psb 4860 data sheet 229 2000-01-14 4d h r dout3 data out (timeslot 3 or static mode) data output data output data for pins ma 0 -ma 11 while ma 15 =1 (only if hwconfig1:app=10). output data for pins ma 0 -ma 15 (only if hwconfig1:app=01) 15 0 data reset value 0
psb 4860 data sheet 230 2000-01-14 4e h din data in (timeslot 3 or static mode) data input data input data for pins ma 0 -ma 11 at falling edge of ma 15 (only if hwconfig1:app=10). input data for pins ma 0 -ma 15 (only if hwconfig1:app=01) 15 0 data
psb 4860 data sheet 231 2000-01-14 4f h r ddir data direction (timeslot 3 or static mode) dir port direction port direction during ma 15 =1 or in static mode. 0: input 1: output 15 0 dir reset value 0 (all inputs)
psb 4860 data sheet 232 2000-01-14 50 h dmask1 data in mask 1 (timeslot 3 or static mode) mask bit mask for falling edge detection if a bit of the mask is set and the corresponding pin is configured as an input, a falling edge at this input will set the ppi bit of the status register. 15 0 mask
psb 4860 data sheet 233 2000-01-14 51 h dmask2 data in mask 2 (timeslot 3 or static mode) mask bit mask for rising edge detection if a bit of the mask is set and the corresponding pin is configured as an input, a rising edge at this input will set the ppi bit of the status register. 15 0 mask
psb 4860 data sheet 234 2000-01-14 52 h r dhold data in hold (timeslot 3 or static mode) data all events, which were not masked by dmask1 or dmask2 register, are collected in this register since the last read access. whenever this register is read it is reset to zero. a bit is subsequently set if an unmasked event happens at the corresponding input pin. 15 0 data
psb 4860 data sheet 235 2000-01-14 53 h scvox1 vox detector 1 nframes number of segments within a frame. cvf minimum number of adjacent voice segments. (cvf=1 means no adjacent voice segments.) 15 0 0 nframes 0 cvf
psb 4860 data sheet 236 2000-01-14 54 h scvox2 vox detector 2 rlpf more than this number of low power segments within a frame classify this frame as low power. rvf minimum number of voice segments within a frame to consider this frame as voice. 15 0 0rlpf0 rvf
psb 4860 data sheet 237 2000-01-14 55 h scvox3 vox detector 3 power the parameter power for a reference power p ([db]) can be calculated by the following formula: 15 0 0power power 32768 p 20 ----- - 10 =
psb 4860 data sheet 238 2000-01-14 56 h scvox4 vox detector 4 crest the parameter crest for a power difference d ([db]) can be calculated by the following formula: 15 0 0 crest power 32768 d ? 20 ----- - 10 =
psb 4860 data sheet 239 2000-01-14 57 h scvox5 vox detector 5 rpowb if there are less than this number of voice slices within a segment this segment is considered as low power. time minimum number of adjacent frames that do not contain cvf voice segments to set the vox bit. 15 0 0rpowb0 time
psb 4860 data sheet 240 2000-01-14 58 h scvox6 vox detector 6 flen number of slices within a segment. 15 0 00000 flen
psb 4860 data sheet 241 2000-01-14 5a h scgap1 speech coder gap control 1 lp2l the parameter lp2l for a saturation level l (db) can be calculated by the following formula: lim the parameter lim for a minimum signal level l (db, relative to pcm max. value) can be calculated by the following formula: 15 0 0lp2l0 lim lp2l 2l 5 log2 ------------------- = lim 2 96.3 l + () 5 log2 ---------------------------------- =
psb 4860 data sheet 242 2000-01-14 5b h scgap2 speech coder gap control 2 lp1 the parameter lp1 for a time t (ms) can be calculated by the following formula: off the parameter off for a level offset of o (db) can be calculated by the following formula: 15 0 lp1 0 off lp1 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; = off 2o 5 log2 ------------------- =
psb 4860 data sheet 243 2000-01-14 5c h scgap3 speech coder gap control 3 pdn the parameter pdn for a time t (ms) can be calculated by the following formula: lp2n the parameter lp2n for a time t (ms) can be calculated by the following formula: 15 0 pdn lp2n pdn 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; = lp2n 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; =
psb 4860 data sheet 244 2000-01-14 5d h scgap4 speech coder gap control 4 pds the parameter pds for a time t (ms) can be calculated by the following formula: lp2s the parameter lp2s for a time t (ms) can be calculated by the following formula: 15 0 pds 0 lp2s pds 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; = lp2s 262144 t ----------------- - =
psb 4860 data sheet 245 2000-01-14 60 h r sctl speakerphone control ens enable echo suppression 0: the echo suppression unit is disabled 1: the echo suppression unit is enabled enc enable echo cancellation 0: the echo cancellation unit is disabled 1: the echo cancellation unit is enabled md mode 0: speakerphone mode 1: loudhearing mode sdr signal source of sdr 0: after agcr 1: before agcr sdx signal source of sdx 0: after agcx 1: before agcx agr agcr enable 0: agcr disabled 1: agcr enabled agx agcx enable 0: agcx disabled 1: agcx enabled 15 0 ensenc000000mdsdrsdx00agragx0 reset value 0000000000000000
psb 4860 data sheet 246 2000-01-14 62 h r ssrc1 speakerphone source 1 i1 input signal selection (acoustic source 1) i2 input signal selection (acoustic source 2) 15 0 000000 i1 i2 reset value 000000 0 0
psb 4860 data sheet 247 2000-01-14 63 h r ssrc2 speakerphone source 2 i3 input signal selection (line source 1) i4 input signal selection (line source 2) 15 0 000000 i3 i4 reset value 000000 0 0
psb 4860 data sheet 248 2000-01-14 64 h ssdx1 speech detector (transmit) 1 lp2l the parameter lp2l for a saturation level l (db) can be calculated by the following formula: lim the parameter lim for a minimum signal level l (db, relative to pcm max. value) can be calculated by the following formula: 15 0 0lp2l0 lim lp2l 2l 5 log2 ------------------- = lim 2 96.3 l + () 5 log2 ---------------------------------- =
psb 4860 data sheet 249 2000-01-14 65 h ssdx2 speech detector (transmit) 2 lp1 the parameter lp1 for a time t (ms) can be calculated by the following formula: off the parameter off for a level offset of o (db) can be calculated by the following formula: 15 0 lp1 0 off lp1 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; = off 2o 5 log2 ------------------- =
psb 4860 data sheet 250 2000-01-14 66 h ssdx3 speech detector (transmit) 3 pdn the parameter pdn for a time t (ms) can be calculated by the following formula: lp2n the parameter lp2n for a time t (ms) can be calculated by the following formula: 15 0 pdn lp2n pdn 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; = lp2n 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; =
psb 4860 data sheet 251 2000-01-14 67 h ssdx4 speech detector (transmit) 4 pds the parameter pds for a time t (ms) can be calculated by the following formula: lp2s the parameter lp2s for a time t (ms) can be calculated by the following formula: 15 0 pds 0 lp2s pds 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; = lp2s 262144 t ----------------- - =
psb 4860 data sheet 252 2000-01-14 68 h ssdr1 speech detector (receive) 1 lp2l the parameter lp2l for a saturation level l (db) can be calculated by the following formula: lim the parameter lim for a minimum signal level l (db, relative to pcm max. value) can be calculated by the following formula: 15 0 0lp2l0 lim lp2l 2l 5 log2 ------------------- = lim 2 96.3 l + () 5 log2 ---------------------------------- =
psb 4860 data sheet 253 2000-01-14 69 h ssdr2 speech detector (receive) 2 lp1 the parameter lp1 for a time t (ms) can be calculated by the following formula: off the parameter off for a level offset of o (db) can be calculated by the following formula: 15 0 lp1 0 off lp1 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; = off 2o 5 log2 ------------------- =
psb 4860 data sheet 254 2000-01-14 6a h ssdr3 speech detector (receive) 3 pdn the parameter pdn for a time t (ms) can be calculated by the following formula: lp2n the parameter lp2n for a time t (ms) can be calculated by the following formula: 15 0 pdn lp2n pdn 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; = lp2n 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; =
psb 4860 data sheet 255 2000-01-14 6b h ssdr4 speech detector (receive) 4 pds the parameter pds for a time t (ms) can be calculated by the following formula: lp2s the parameter lp2s for a time t (ms) can be calculated by the following formula: 15 0 pds 0 lp2s pds 64 t ? 0.5 t 64 << ; 128 2048 t ? + 16.2 t 2048 << ; = lp2s 262144 t ----------------- - =
psb 4860 data sheet 256 2000-01-14 6c h sscas1 speech comparator (acoustic side) 1 g the parameter g for a gain a (db) can be calculated by the following formula: note: the parameter g is interpreted in two?s complement. et the parameter et for a time t (ms) can be calculated by the following formula: 15 0 get g 2a 5 log2 ------------------- = et t 4 -- - =
psb 4860 data sheet 257 2000-01-14 6d h sscas2 speech comparator (acoustic side) 2 gdn the parameter gdn for a gain g (db) can be calculated by the following formula: pdn the parameter pdn for a decay rate r (ms/db) can be calculated by the following formula: 15 0 0gdn pdn gdn 4g 5 log2 ------------------- = pdn 64 5 log2 r ----------------------------- - =
psb 4860 data sheet 258 2000-01-14 6e h sscas3 speech comparator (acoustic side) 3 gds the parameter gds for a gain g (db) can be calculated by the following formula: pds the parameter pds for a decay rate r (ms/db) can be calculated by the following formula: 15 0 0gds pds gds 4g 5 log2 ------------------- = pds 64 5 log2 r ----------------------------- - =
psb 4860 data sheet 259 2000-01-14 6f h sscls1 speech comparator (line side) 1 g the parameter g for a gain a (db) can be calculated by the following formula: note: the parameter g is interpreted in two?s complement. et the parameter et for a time t (ms) can be calculated by the following formula: 15 0 get g 2a 5 log2 ------------------- = et t 4 -- - =
psb 4860 data sheet 260 2000-01-14 70 h sscls2 speech comparator (line side) 2 gdn the parameter gdn for a gain g (db) can be calculated by the following formula: pdn the parameter pdn for a decay rate r (ms/db) can be calculated by the following formula: 15 0 0gdn pdn gdn 4g 5 log2 ------------------- = pdn 64 5 log2 r ----------------------------- - =
psb 4860 data sheet 261 2000-01-14 71 h sscls3 speech comparator (line side) 3 gds the parameter gds for a gain g (db) can be calculated by the following formula: pds the parameter pds for a decay rate r (ms/db) can be calculated by the following formula: 15 0 0gds pds gds 4g 5 log2 ------------------- = pds 64 5 log2 r ----------------------------- - =
psb 4860 data sheet 262 2000-01-14 72 h satt1 attenuation unit 1 att the parameter att for an attenuation a (db) can be calculated by the following formula: sw the parameter sw for a switching rate r (ms/db) can be calculated by the following formula: 15 0 0att sw att 2a 5 log2 ------------------- = sw 128 1 5log2 r ----------------------------- - + 0.0053 r 0.66 << ; 16 5log2 r ----------------------------- - 0.66 r 0.63 << ; =
psb 4860 data sheet 263 2000-01-14 73 h satt2 attenuation unit 2 tw the parameter tw for a time t (ms) can be calculated by the following formula: ds the parameter ds for a decay rate r (ms/db) can be calculated by the following formula: note: the value 0xff for the parameter ds specifies an infinite decay rate. therefore the speakerphone will not return to the idle state in the absence of s peech signals. it will remain in the current state until a speech signal is detected and a state change is necessary. 15 0 tw ds tw t 16 ----- - = ds 5 log2 r1 ? 4 -------------------------------------- - =
psb 4860 data sheet 264 2000-01-14 74 h sagx1 automatic gain control (transmit) 1 ag_init the parameter ag_init for a gain g (db) can be calculated by the following formula: note: this parameter is interpreted in two ? s complement. com the threshold com for a level l (db) can be calculated by the following formula: 15 0 ag_init 0 com ag_init 2 ? g 5log2 ------------------- = com 2 96.3 l + () 5 log2 ---------------------------------- =
psb 4860 data sheet 265 2000-01-14 75 h sagx2 automatic gain control (transmit) 2 ag_att the parameter ag_att for a gain g (db) can be calculated by the following formula: speedh the parameter speedh for the regulation speed r (ms/db) can be calculated by the following formula: the variable d denotes the aberration (db). 15 0 0 ag_att speedh ag_att 2 ? g 5 log2 ------------------- = speedh 512 dr -------------- =
psb 4860 data sheet 266 2000-01-14 76 h sagx3 automatic gain control (transmit) 3 ag_gain the parameter ag_gain for a gain g (db) can be calculated by the following formula: speedl the parameter speedl for the regulation speed r (ms/db) can be calculated by the following formula: the variable d denotes the aberration (db). 15 0 ag_gain speedl ag_gain 2 ? g 5 log2 ------------------- = speedl 4096 dr -------------- =
psb 4860 data sheet 267 2000-01-14 77 h sagx4 automatic gain control (transmit) 4 nois the parameter nois for a threshold level l (db) can be calculated by the following formula: lpa the parameter lpa for a low pass time constant t (ms) can be calculated by the following formula: 15 0 0nois0 lpa nois 296.3l + () 5 log2 ---------------------------------- = lpa 16 t ----- - =
psb 4860 data sheet 268 2000-01-14 78 h sagx5 automatic gain control (transmit) 5 ag_cur the current gain g (db) of the agc can be derived from the parameter parameter ag_cur by the following formula: note: ag_cur is interpreted in two ? s complement. 15 0 ag_cur 00000000 g 5 ? log2 ag_cur 2 ----------------------------------------------------- =
psb 4860 data sheet 269 2000-01-14 79 h sagr1 automatic gain control (receive) 1 ag_init the parameter ag_init for a gain g (db) can be calculated by the following formula: note: this parameter is interpreted in two ? s complement. com the parameter com for a threshold l (db) can be calculated by the following formula: 15 0 ag_init 0 com ag_init 2 ? g 5log2 ------------------- = com 2 96.3 l + () 5 log2 ---------------------------------- =
psb 4860 data sheet 270 2000-01-14 7a h sagr2 automatic gain control (receive) 2 ag_att the parameter ag_att for a gain g (db) can be calculated by the following formula: speedh the parameter speedh for the regulation speed r (ms/db) can be calculated by the following formula: the variable d denotes the aberration (db). 15 0 0 ag_att speedh ag_att 2 ? g 5 log2 ------------------- = speedh 512 dr -------------- =
psb 4860 data sheet 271 2000-01-14 7b h sagr3 automatic gain control (receive) 3 ag_gain the parameter ag_gain for a gain g (db) can be calculated by the following formula: speedl the parameter speedl for the regulation speed r (ms/db) can be calculated by the following formula: the variable d denotes the aberration (db). 15 0 ag_gain speedl ag_gain 2 ? g 5 log2 ------------------- = speedl 4096 dr -------------- =
psb 4860 data sheet 272 2000-01-14 7c h sagr4 automatic gain control (receive) 4 nois the parameter nois for a threshold level l (db) can be calculated by the following formula: lpa the parameter lpa for a low pass time constant t (ms) can be calculated by the following formula: 15 0 0nois0 lpa com 2 96.3 l + () 5 log2 ---------------------------------- = lpa 16 t ----- - =
psb 4860 data sheet 273 2000-01-14 7d h sagr5 automatic gain control (receive) 5 ag_cur the current gain g (db) of the agcr can be derived from the parameter ag_cur by the following formula: note: ag_cur is interpreted in two ? s complement. 15 0 ag_cur 00000000 g 5 ? log2 ag_cur 2 ----------------------------------------------------- =
psb 4860 data sheet 274 2000-01-14 7e h slga line gain lgar the parameter lgar for a gain g (db) is given by the following formula: lgax the parameter lgax for a gain g (db) is given by the following formula: 15 0 0lgar0lgax lgar 128 g12 ? () 20 ? 10 = lgax 128 g12 ? () 20 ? 10 =
psb 4860 data sheet 275 2000-01-14 80 h saelen acoustic echo cancellation length len len denotes the number of fir-taps used. recommended values are: 127, 255, 383, 511 15 0 0000000 len
psb 4860 data sheet 276 2000-01-14 81 h saeatt acoustic echo cancellation double talk attenuation att the parameter att for an attenuation a (db) is given by the following formula: 15 0 0att att 512 a 5 log2 ------------------- =
psb 4860 data sheet 277 2000-01-14 82 h saegs acoustic echo cancellation global scale gs all coefficients of the fir filter are scaled by a factor c. this factor is given by the following equation: 15 0 0000000000000 gs c2 gs =
psb 4860 data sheet 278 2000-01-14 83 h saeps1 acoustic echo cancellation partial scale ps the additional scaling coefficient ac is given by the following formula: 15 0 0000000000000 ps ac 2 ps =
psb 4860 data sheet 279 2000-01-14 84 h saeps2 acoustic echo cancellation first block fb the parameter fb denotes the first block that is affected by the partial scaling coefficient. if the partial coefficient is one, fb is disregarded. 15 0 0000000000000 fb
psb 4860 data sheet 280 2000-01-14 9a h r cidmf1 caller id message format mf message format valid start byte. 15 0 0mf reset value 00
psb 4860 data sheet 281 2000-01-14 9b h r cidmf2 caller id message format mf message format valid start byte. 15 0 0mf reset value 00
psb 4860 data sheet 282 2000-01-14 9c h r cidmf3 caller id message format mf message format valid start byte. 15 0 0mf reset value 00
psb 4860 data sheet 283 2000-01-14 9d h r cidmf4 caller id message format mf message format valid start byte. 15 0 0mf reset value 00
psb 4860 data sheet 284 2000-01-14 9e h r cidmf5 caller id message format mf message format valid start byte. 15 0 0mf reset value 00
psb 4860 data sheet 285 2000-01-14 9f h r cidmf6 caller id message format mf message format valid start byte. 15 0 0mf reset value 00
psb 4860 data sheet 286 2000-01-14 a0 h r utdctl universal tone detector control en utd detector enable 0: disabled 1: enabled i1 input signal selection 15 0 en0000000000 i1 reset value 00000000000 0
psb 4860 data sheet 287 2000-01-14 a1 h utdcf center frequency for utd cf the parameter cf for a center frequency f (hz) can be calculated by the following formula: note: the parameter cf is implemented in two ? s complement. 15 0 cf cf 32768 2 f 8000 -------------------- cos =
psb 4860 data sheet 288 2000-01-14 a2 h utdbw band width for utd bw the parameter bw for a band width b (hz) can be calculated by the following formula: 15 0 0bw bw 65536 b 8000 ? () tan 1 b 8000 ? () tan + --------------------------------------------------- - =
psb 4860 data sheet 289 2000-01-14 a3 h utdlim limiter limit for utd lim signal limit the parameter lim for a limit of l[db] can be calculated by the following formula: 15 0 0lim lim 32768 l20 ? 10 =
psb 4860 data sheet 290 2000-01-14 a4 h utdlev minimal signal level for utd lev minimal level of signal the parameter lev for a minimum in-band signal level of l[db] can be calculated by the following formula: 15 0 0lev lev 32768 l20 ? 10 =
psb 4860 data sheet 291 2000-01-14 a5 h utddlt minimum difference for utd delta minimal difference between in-band signal and out-of-band signal the parameter delta for a signal difference of d [db] can be calculated by the following formula: 15 0 delta delta d () sgn 32768 d () 20 ? ? 10 =
psb 4860 data sheet 292 2000-01-14 a6 h utdtmt tone times for utd ttone minimum time for activation the parameter ttone for a minimal activation time t [ms] can be calculated by the following formula: tb1 maximum break time for ttone the parameter tb1 for a maximum break time is given in milliseconds. 15 0 ttone tb1 ttone t 8 -- - =
psb 4860 data sheet 293 2000-01-14 a7 h utdtmg gap times for utd tgap minimum time for deactivation the parameter tgap for a minimal deactivation time t [ms] can be calculated by the following formula: tb2 maximum break time for tgap the parameter tb2 for a maximum break time is given in milliseconds. 15 0 tgap tb2 tgap t 8 -- - =
psb 4860 data sheet 294 2000-01-14 aa h r cisctl caller id sender control en caller id sender enable 0: disabled 1: enabled md mode 0: v.23 1: bellcore 15 0 enmd00000000000000 reset value 0000000000000000
psb 4860 data sheet 295 2000-01-14 ab h cisdata data byte for caller id sender data data byte to send a write access to this registers resets the status bits cis and cir. 15 0 00000000 data
psb 4860 data sheet 296 2000-01-14 ac h cislev level of signal for caller id sender lev signal level the parameter lev for a level of l [db] can be calculated by the following formula: 15 0 0lev lev 32768 l6 + () 20 ? 10 =
psb 4860 data sheet 297 2000-01-14 ad h cisszr number of seizure bits seiz number of seizure bits the number of seizure bits to be sent before a data transmission. 15 0 0 seiz
psb 4860 data sheet 298 2000-01-14 ae h cismrk number of mark bits mark number of mark bits the number of mark bits to be sent before a data transmission. 15 0 0mark
psb 4860 data sheet 299 2000-01-14 4 electrical characteristics electrical characteristics electrical characteristics 4.1 absolute maximum ratings esd integrity (according mil-std. 883d, method 3015.7): 2 kv exception: the pins int , sdx, du/dx, dd/dr, sps 0 , sps 1 and md 0 -md 7 are not protected against voltage stress >1 kv. note: conditions: maximum ratings are stress ratings only, and functional operation and reliability under conditions beyond those defined in the "recommended operating conditions" is not guaranteed. stresses above the maximum ratings are likely to cause permant damage. 4.2 dc characteristics parameter symbol limit values unit ambient temperature under bias t a -20 to 85 c storage temperature t stg ? 65 to125 c supply voltage v dd -0.5 to 4.2 v supply voltage v dda -0.5 to 4.2 v voltage of pin with respect to ground: osc 1 , osc 2 , xtal 1 , xtal 2 v s 0 to v dda v voltage on any pin with respect to ground (except osc 1 , osc 2 , xtal 1 , xtal 2 ) v s ? 0.4 to 5.5 1) 1) the difference from the minumum to the maximum value for v s /v dd /v ss at any pin must never exceed 5.5 v. v v dd / v dda = 3.3 v 0.3 v; v ss / v ssa = 0 v; t a = 0 to 70 c parameter symbol limit values unit test condition min. typ. max. input leakage current i il ? 5.0 5.0 a0v v in v dd h-input level (except ma 0 -ma 15 , xtal 1 , osc 1 ) v ih1 2.0 5.5 1) v h-input level (xtal 1 , osc 1 ) v ih2 0.8 v dd v dda + 0.3 v h-input level (ma 0 -ma 15 , mctl 2) ) v ih3 2.0 v dd + 0.3 v l-input level (except pins xtal 1 ,osc 1 ) v il1 ? 0.3 0.8 v
psb 4860 data sheet 300 2000-01-14 4.3 ac characteristics digital inputs are driven to 2.4 v for a logical ? 1 ? and to 0.45 v for a logical ? 0 ? . timing measurements are made at 2.0 v for a logical ? 1 ? and 0.8 v for a logical ? 0 ? . the ac- testing input/output waveforms are shown below. l-input level (xtal 1 , osc 1 ) v il2 ? 0.3 0.2 v dda v h-output level (except du/dx, dd/ dr, ma 0 -ma 15 ) v oh1 v dd ? 0.45 v i o = 2 ma h-output level (ma 0 -ma 15 ) v oh3 v dd ? 0.45 v i o = 5 ma h-output level (du/dx, dd/dr) v oh4 v dd ? 0.45 v i o = 7 ma l-output level (except du/dx, dd/ dr, ma 0 -ma 15 ) v ol1 0.45 v i o = ? 2 ma l-output level (ma 0 -ma 15 ) (address mode or app output) v ol2 0.45 v i o = ? 5 ma l-output current (ma 0 -ma 15 ) (after reset) i lo 55 102 200 arst=1 h-output current (mctl 1) ) i ho 55 100 157 arst=1 l-output level (pins du/dx, dd/ dr) v ol3 0.45 v i o = ? 7 ma internal pullup current (frdy ) i li 370 680 950 a input capacitance c i 10 pf output capacitance c o 15 pf v dd + v dda supply current (power down, no refresh, no rtc) i dds1 10 50 a v dd + v dda supply current operating i ddo 50 60 ma v dd = 3.3 v 1) the difference from the minumum to the maximum value for v s /v dd /v ss at any pin must never exceed 5.5 v. 2) mctl signals are (w /fwe , vprd /fcle, ras /foe , cas 0 /ale, cas 1 /fcs ) v dd / v dda = 3.3 v 0.3 v; v ss / v ssa = 0 v; t a = 0 to 70 c parameter symbol limit values unit test condition min. typ. max.
psb 4860 data sheet 301 2000-01-14 figure 81 input/output waveforms for ac-tests
psb 4860 data sheet 302 2000-01-14 dtmf detector parameter symbol limit values unit test condition min. typ. max. frequency deviation accept -1.5 1.5 % frequency deviation reject 3.5 -3.5 % acceptance level -45 0 db rel. to max. pcm rejection level -50 db rel. to max. pcm twist deviation accept +/-2 +/-8 db programmable noise tolerance 12 db signal duration accept 40 ms signal duration reject 23 ms gap duration accept 40 ms gap duration reject 23 ms cpt detector parameter symbol limit values unit test condition min. typ. max. frequency acceptance range 300 640 hz frequency rejection range 800 200 hz acceptance level -45 0 db rel. to max. pcm rejection level -50 db rel. to max. pcm signal duration accept 50 ms programmable signal duration reject 10 ms caller id decoder parameter symbol limit values unit test condition min. typ. max. frequency deviation accept -2 2 % acceptance level -45 0 db rel. to max. pcm transmission rate 1188 1200 1212 baud noise tolerance (cm=1), out of band -12 db noise tolerance (cm=1), in band 25 db 200 to 3200 hz
psb 4860 data sheet 303 2000-01-14 alert tone detector parameter symbol limit values unit test condition min. typ. max. frequency deviation accept -0.5 0.5 % atdctl1:dev=0 frequency deviation accept -1.1 1.1 % atdctl1:dev=1 frequency deviation reject 3.5 -3.5 % acceptance level -40 0 db rel. to max. pcm rejection level -5 db rel. to acceptance level twist deviation accept +/-7 db noise tolerance 20 db signal duration accept 75 ms gap duration accept (off-hook) 50 ms atdctl1:onh=0 gap duration accept (on-hook) 16 ms atdctl1:onh=1 cng detector parameter symbol limit values unit test condition min. typ. max. frequency deviation accept -30 30 hz frequency deviation reject -50 50 hz acceptance level -45 0 db snr >10 db acceptance level -50 0 db snr >15 db rejection level -5 db db rel. to cnglev:min signal duration reject -1 % rel. to cngbt:time
psb 4860 data sheet 304 2000-01-14 status register update time the individual bits of the status register may change due to an event (like a recognized dtmf tone) or a command. the timing can be divided into four classes with these definitions the timing of the individual bits in the status register can be given as shown in table: table 108 status register update timing class timing comment min. max. i 0 0 immediately after command has been issued a 0 150 s 1) 1) 250 us if speakerphone enabled command has been accepted e - - associated event has happened bit rdy abt cia cd cpt cng sd err bsy dtv atv 0->1 aeeeeeeeaee 1->0 i a ae,ae,aae,aa ee,ae,a bit gap vox pqe ppi 0->1 eeee 1->0 e,a e,a e a
psb 4860 data sheet 305 2000-01-14 figure 82 oscillator circuits note: this generally recommended circuity and the values must be verified for each board design. please use the appropriate application note for doing so. furthermore, the provider of the crystal must be consulted for verification of the circuitry. recommended / maximum values oscillator circuit value unit min typ max main oscillator crystal load capacitance c l 12 ext. capacitors ca 1 = ca 2 @ 34.560mhz 5 8.2 12 pf ext. capacitors ca 1 = ca 2 @ 31.104mhz 5 10 15 pf static (parallel) capacitance x 1 7pf resonance resistance x 1 40 ? frequency deviation 500 1) 1) the frequency deviation must not exceed 500 ppm if afe clock tracking (bit act in register hwconfig1) is enabled. ppm auxilliary oscillator (f = 32.768khz) crystal load capacitance c l 10 pf ext. capacitors cb 1 = cb 2 520pf static capacitance x 2 3pf resonance resistor x 2 40 k ? xtal 1 xtal 2 c a1 c a2 x 1 osc 1 osc 2 c b1 c b2 x 2 main oscillator auxilliary oscillator
psb 4860 data sheet 306 2000-01-14 figure 83 ssdi/iom ? -2 interface - bit synchronization timing figure 84 ssdi/iom ? -2 interface - frame synchronization timing parameter ssdi/iom ? -2 interface symbol limit values unit min max dcl period t 1 90 ns dcl high t 2 35 ns dcl low t 3 35 ns input data setup t 4 20 ns dd/dr dcl du/dx du/dx first bit last bit bit n bit n+1 t 4 t 6 t 7 t 8 t 5 t 2 t 1 t 3 fsc dcl t 9 t 10 t 9 t 10
psb 4860 data sheet 307 2000-01-14 input data hold t 5 20 ns output data from high impedance to active (fsc high or other than first timeslot) t 6 30 ns output data from active to high impedance t 7 30 ns output data delay from clock t 8 30 ns fsc setup t 9 40 ns fsc hold t 10 40 ns fsc jitter (deviation per frame) -200 200 ns parameter ssdi/iom ? -2 interface symbol limit values unit min max
psb 4860 data sheet 308 2000-01-14 figure 85 ssdi interface - strobe timing parameter ssdi interface symbol limit values unit min max dxst delay t 1 20 ns drst inactive setup t 2 20 ns drst inactive hold t 3 20 ns drst active setup t 4 20 ns drst active hold t 5 20 ns fsc setup t 6 8 dcl cycles fsc hold t 7 40 ns drst dcl t 4 t 5 t 2 t 3 fsc t 6 t 7 dxst t 1
psb 4860 data sheet 309 2000-01-14 figure 86 serial control interface parameter sci interface symbol limit values unit min max sclk cycle time t 1 500 ns sclk high time t 2 100 ns sclk low time t 3 100 ns cs setup time t 4 40 ns cs hold time t 5 10 ns sdr setup time t 6 40 ns sdr hold time t 7 40 ns sdx data out delay t 8 80 ns cs high to sdx tristate t 9 40 ns sclk to sdx active t 10 80 ns sclk to sdx tristate t 11 40 ns cs to int delay t 12 80 ns cs sclk sdr sdx int t 4 t 2 t 3 t 1 t 12 t 10 t 11 t 9 t 5 t 6 t 7 t 8
psb 4860 data sheet 310 2000-01-14 figure 87 analog front end interface parameter afe interface symbol limit values unit min max afeclk period t 1 125 165 ns afeclk high t 2 21/f xtal afeclk low t 3 21/f xtal afedu setup t 4 20 ns afedu hold t 5 20 ns afedd output delay t 6 30 ns afefs output delay t 7 30 ns afedu afeclk afedd bit n bit n+1 t 4 t 6 t 5 t 2 t 1 t 3 afefs t 7 t 7
psb 4860 data sheet 311 2000-01-14 figure 88 memory interface - dram read access parameter memory interface - dram read access symbol limit values unit min max row address setup time t 1 50 ns row address hold time t 2 50 ns column address setup time t 3 50 ns ras precharge time t 4 110 ns ras to cas delay t 5 110 2000 ns cas pulse width t 6 110 2000 ns data input setup time t 7 40 ns data input hold time t 8 0ns ma 0 -ma 13 md 0 -md 7 cas 0 ,cas 1 ras row addr. col. addr. t 1 t 2 t 3 t 6 t 7 t 8 t 5 t 4
psb 4860 data sheet 312 2000-01-14 figure 89 memory interface - dram write access parameter memory interface - dram write access symbol limit values unit min max row address setup time t 1 50 ns row address hold time t 2 50 ns column address setup time t 3 50 ns ras precharge time t 4 110 ns ras to cas delay t 5 110 2000 ns cas pulse width t 6 110 2000 ns data output setup time t 7 100 ns data output hold time t 8 50 ns ras to w delay t 9 50 ns w to cas setup t 10 50 ns ma 0 -ma 13 md 0 -md 7 cas 0 ,cas 1 ras row addr. col. addr. t 1 t 2 t 3 t 6 t 7 t 8 t 5 t 4 w t 9 t 10
psb 4860 data sheet 313 2000-01-14 figure 90 memory interface - dram refresh cycle note: the frequency of the dram refresh cycle depends on the selected mode. in active mode or normal refresh mode (during power down) the minimal frequency is 64 khz. in battery backup mode, the refresh frequency is 8 khz. parameter memory interface - dram refresh cycle symbol limit values unit min max ras precharge time t 1 100 ns ras low time t 2 200 5000 ns cas setup t 3 100 ns cas hold t 4 100 ns cas 0 ,cas 1 ras t 3 t 1 t 2 t 4
psb 4860 data sheet 314 2000-01-14 figure 91 memory interface - eprom read parameter memory interface - eprom read symbol limit values unit min max address setup before vprd t 1 110 ns vprd low time t 2 500 ns data setup time t 3 40 ns data hold time t 4 0ns ma 0 -ma 15 md 0 -md 7 vprd linear address t 1 t 2 t 3 t 4
psb 4860 data sheet 315 2000-01-14 figure 92 memory interface - samsung command write note: fcs stays low if other cycles follow for the same access. parameter memory interface - samsung command write symbol limit values unit min max address setup before fcs , fcle t 1 100 ns fcs low time, fcle high time t 2 400 ns fwr hold after fcle rising t 3 100 ns fwr low time t 4 200 ns fwr setup before fcle falling t 5 100 ns data setup time t 6 200 ns data hold time t 7 50 ns ma 0 -ma 11 md 0 -md 7 fcs (fcs 0 -fcs 3 ) a 16 -a 23 and fcs 0 -fcs 3 t 1 t 2 fwr fcle t 3 t 4 t 5 t 6 t 7
psb 4860 data sheet 316 2000-01-14 figure 93 memory interface - samsung address write parameter memory interface - samsung address write symbol limit values unit min max ale high time t 1 400 ns fwr hold after ale rising t 2 100 ns fwr low time t 3 200 ns fwr setup before ale falling t 4 100 ns data setup time t 5 200 ns data hold time t 6 50 ns md 0 -md 7 t 1 fwr ale t 2 t 3 t 4 t 5 t 6
psb 4860 data sheet 317 2000-01-14 figure 94 memory interface - samsung data write parameter memory interface - samsung data write symbol limit values unit min max fwr low time t 1 200 ns data setup time t 2 200 ns data hold time t 3 50 ns md 0 -md 7 fwr t 1 t 2 t 3
psb 4860 data sheet 318 2000-01-14 figure 95 memory interface - samsung data read parameter memory interface - samsung data read symbol limit values unit min max foe low time t 1 200 ns data setup time t 2 40 ns data hold time t 3 0ns md 0 -md 7 foe t 1 t 2 t 3
psb 4860 data sheet 319 2000-01-14 figure 96 auxiliary parallel port - multiplex mode parameter auxiliary port interface - multiplex mode symbol limit values unit min typ max active time (ma 0 -ma 15 ) t 1 2ms gap time (ma 0 -ma 15 ) t 2 125 s data setup time t 3 50 ns data hold time t 4 0ns ma 0 -ma 11 ma 12 t 3 t 4 t 1 t 2 ma 13
psb 4860 data sheet 320 2000-01-14 figure 97 reset timing parameter reset timing symbol limit values unit min max v dd / v ddp / v dda rise time 5%-95% t 1 20 ms supply voltages stable to rst high t 2 0ns supply voltages stable to rst low t 3 0.1 ms rst high time t 4 1000 ns rst t 3 v dd / v ddp t 1 t 2 t 4
psb 4860 data sheet 321 2000-01-14 5 package outlines plastic package, p-mqfp-80 (smd) (plastic metric quad flat package) sorts of packing package outlines for tubes, trays etc. are contained in our data book ? package information ? . dimensions in mm smd = surface mounted device
psb 4860 data sheet 322 2000-01-14 a abort clearing event 104 , 153 functional description 104 status bit 141 alert tone detector electrical characteristics 303 functional description 50 registers 181 ? 182 status bit 142 analog front end interface electrical characteristics 310 functional description 69 registers 157 ? 163 timing 117 aram see memory interface automatic gain control functional description 73 registers 209 ? 215 auxiliary parallel port electrical characteristics 319 mode bits 145 multiplex mode 137 registers 226 ? 231 static mode 137 c caller id decoder electrical characteristics 302 functional description 55 , 57 registers 183 ? 184 status bits 141 ? 142 cng detector electrical characteristics 303 functional description 49 registers 177 ? 180 status bit 142 cpt detector electrical characteristics 302 functional description 53 registers 187 ? 191 , 221 ? 222 status bit 142 d digital interface functional description 70 mode bits 145 registers 164 ? 186 dram see memory interface dtmf detector electrical characteristics 302 functional description 48 registers 196 ? 198 status bit 142 dtmf generator functional description 59 registers 172 ? 176 e eprom see memory interface equalizer functional description 75 registers 199 ? 201 execution times file commands 98 f file commands access file descriptor 92 compress 90 create next new 88 delete 89 ? 90 execution times 98 new file 87 open 87 read binary data 86 , 93 registers 216 ? 220 restrictions 99 seek 89 status bits 142 tailcut 89 ? 90 write binary data 93 type audio 80 binary 81
psb 4860 data sheet 323 2000-01-14 phrase 81 user data word 82 ? 83 flash memory see memory interface g group listening 41 h hardware configuration functional description 104 registers 144 i interrupt functional description 102 pin configuration 144 register 156 iom ? -2 interface electrical characteristics 306 ? 307 functional description 111 see also: digital interface l line echo canceller functional description 45 registers 192 ? 195 loudhearing 41 m memory interface aram/dram connection diagram 127 electrical characteristics 311 ? 313 refresh 129 , 146 timing 128 eprom connection diagram 130 electrical characteristics 314 timing 130 flash connection diagram 131 , 135 electrical characteristics 315 ? 318 in-circuit programming 125 , 146 multiple devices 132 timing 133 register 154 supported devices 125 memory management activation 85 directories 79 ? 80 executiontimes 98 files 80 garbage collection 91 initialization 83 ? 84 memory status 91 overview 79 status 82 o oscillator electrical characteristics 305 mode bits 145 p power down functional description 102 status bit 144 r real time clock configuration bits 144 functional description 101 oscillator 305 registers 224 ? 225 recompression 90 reset electrical characteristics 320 functional description 102 register values 148 restrictions file commands 99 modules 106 revision functional description 104 register 153 s serial control interface command opcodes 110 , 122 electrical characteristics 309 functional description 119 signals
psb 4860 data sheet 324 2000-01-14 encoding 151 reference table 151 speakerphone functional description automatic gain control 41 control 40 echo cancellation 30 echo suppression 32 overview 29 speech comparator 37 speech detector 34 registers 245 ? 278 speech coder functional description 60 registers 202 ? 208 speech decoder functional description 66 register 206 sps outputs functional description 41 , 101 register 223 ssdi interface electrical characteristics 306 ? 308 functional description 115 see also: digital interface status register definition 141 update timing 304 u universal attenuator functional description 72 register 171

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